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VERFAHREN ZUR DEMODULATION UND DECODIERUNG VON MLS-DPSK-SENDUNGEN UNTER VERWENDUNG VON EINEM DIGITALEN SIGNALPROZESSOR. - Dokument EP0539526
 
PatentDe  


Dokumentenidentifikation EP0539526 12.01.1995
EP-Veröffentlichungsnummer 0539526
Titel VERFAHREN ZUR DEMODULATION UND DECODIERUNG VON MLS-DPSK-SENDUNGEN UNTER VERWENDUNG VON EINEM DIGITALEN SIGNALPROZESSOR.
Anmelder Allied-Signal Inc., Morristown, N.J., US
Erfinder LABERGE, Edward, Francois, Charles, Towson, MD 21204, US;
VANCE, Daniel, Lawrence, Edgewood, MD 21040, US
Vertreter derzeit kein Vertreter bestellt
DE-Aktenzeichen 69105508
Vertragsstaaten DE, FR, GB, IT
Sprache des Dokument En
EP-Anmeldetag 09.05.1991
EP-Aktenzeichen 919164053
WO-Anmeldetag 09.05.1991
PCT-Aktenzeichen US9103216
WO-Veröffentlichungsnummer 9201948
WO-Veröffentlichungsdatum 06.02.1992
EP-Offenlegungsdatum 05.05.1993
EP date of grant 30.11.1994
Veröffentlichungstag im Patentblatt 12.01.1995
IPC-Hauptklasse G01S 1/56
IPC-Nebenklasse H04L 27/22   

Beschreibung[en]
Background of the Invention Field of the Invention

The present invention relates to the Microwave Landing System. More particularly the present invention relates to detecting, demodulating and decoding the Differential Phase Shift Keying (DPSK) transmissions of function identification and data transmissions associated with the international standard Microwave Landing System (MLS).

Description of the Prior Art

The Microwave Landing System (MLS) is an internationally standardized means to provide precision approach and landing guidance to properly equipped user aircraft. The MLS signal format as illustrated in Figures 1 - 3 consists of a series of guidance and data functions transmitted in a time-division-multiplex (TDM) signal format on a single one of 200 channels in the microwave C-band (5030-5090 Mhz). The signal format is radiated by ground stations located at the airport and received by special equipment within the user aircraft.

Each MLS function slot is identified by a unique digital code transmitted as part of the function preamble using DPSK encoding. Each digital bit is 64 usec (microsecond) wide, for an effective data rate of 15,625 bits/sec.

The function preamble for all MLS functions is divided into at least three sections, as shown in Figure 4. The first 13 bit period (832 usec) consists of an unmodulated carrier which is equivalent to a string of binary zeros encoded into DPSK. This is followed by a five bit digital Barker Code (11101) for time synchronization. Finally, a unique seven bit function identification code, consisting of five data and two parity bits, is sent to identify the ensuing MLS function.

Many classical texts on communications theory such as Communication Systems and Techniques, by Schwartz, M., Bennett, W.R., and Stein, S., McGraw - Hill Book Co., New York, 1966, illustrate the simple, straightforward means of DPSK decoding shown in Figure 5. In this approach, a delayed version of the received signal is used as the reference oscillator in a coherent detector. The coherent detector output is proportional to the phase difference between this reference and the current received signal, i.e., between the current and previous DPSK bits. The actual numerical output of the coherent detector depends on the total electrical phase of the intermediate frequency (IF) signal, wifT, over the period, T, of a single DPSK bit, where wif is the angular frequency of the IF signal in radians/sec and T is measured in seconds.

As noted in Communication Systems and Techniques (cited above) and elsewhere, this technique is applicable only in cases where the frequency error in wif is small. If the frequency error, εif, is not small, the total phase (wif+ εif)T can vary significantly from the expected result. In the extremes, the output of the coherent detector in Figure 5 could be zero (when (wifif)T = π/2) or the state of the information bits could be reversed (when (wifif)T=π).

In the MLS application, even a perfect receiver could experience frequency errors which exceed these limits, due to ground station frequency stability and aircraft motion doppler. This is discussed in Annex 10 to the Convention on International Civil Aviation, Volume 1, Chapter 3.11, ICAO, Montreal, Oct. 1987, as well as Minimum Operational Performance Standards for Microwave Landing System Airborne Receiving Equipment, DO-177, Change 2, RTCA, Washington, D.C., Sept. 1986. Thus, the classical approach to DPSK demodulation will not produce the desired performance under typical MLS operating conditions.

A system for demodulating and decoding differential phase shift keying transmissions comprising bandpass filter means for receiving analog signals and for providing filtered analog signals to signal processor means generating information representing demodulated and decoded differential phase shift keying transmissions and provided with phase tracking and phase correction capabilities has already been proposed. More particularly an implementation of such prior system which has been successfully used in MLS receivers is shown in Figure 6. In this approach, the input signal is used to drive a phased-locked carrier regeneration loop which provides an unmodulated local oscillator signal as a phase reference. The coherent detector output is then converted from DPSK to binary information by means of a simple digital circuit. The key feature of this previously demonstrated implementation is that the phase tracking is performed at the IF frequency, before demodulation of the DPSK information. This implementation has been very successful in MLS applications, but it requires additional hardware to implement the phase locked loop.

Previous patents in MLS signal processing such as U.S. Patent No. 4,489,326 to Studenny and U.S. Patent No. 4,017,862 to Wild, have centered on the decoding of the proportional angle guidance information by means of a variety of microprocessor-aided techniques. U.S. Patent No. 4,926,186 by Kelly and La Berge and assigned to the same assignee as the present invention provides a hardware intensive computation architecture which is appropriate for applications requiring sampled data rates in excess of those easily handled in software. The present invention extends the use of a microprocessor- or digital signal processor- aiding to the phase demodulation process. Use of the described implementation allows the entire MLS decoding process to be performed within an existing microprocessor or computer, eliminating the need for relatively costly and relatively unreliable phase-locked loops for carrier regeneration. The present invention can be utilized in highly reliable MLS receiver architectures, including the Integrated Communications, Navigation, Identification (ICNI) electronics now being designed for advanced fighter aircraft and the Military Microwave Landing System Avionics program.

Summary of the Invention

The present invention as defined in independent claim 1 and independent method claim 6 detects, demodulates and decodes the Differential Phase Shift Keying (DPSK) transmissions of function identification and data transmission associated with the international standard Microwave Landing System (MLS). The design involves (1) resolution of a sampled intermediate frequency signal into a complex signal of in-phase and quadrature components by digital means, (2) coherent detection of the DPSK modulation, (3) phase tracking of the detected signal, and (4) discrimination for proper MLS signal characteristics.

In more detail the present invention provides the necessary system design parameters to allow proper decoding of MLS DPSK information. It includes application of a previously described technique which provides in-phase and quadrature outputs without additional hardware, to samples of an IF signal. This previously described technique is described in "A Simple Method for Sampling In-Phase and Quadrature Components", Rader, C.M., IEEE Transactions on Aerospace and Electronic Systems, Vol. AES-20, No. 6, November 1984. The present invention provides for a straightforward arithmetic computation to establish the average phase difference between complex samples separated by a single DPSK bit time, T, of 64 usec. It provides for tracking and removing the residual phase component wT, by using the carrier acquisition period of the MLS signal format. Finally, it provides a series of validation checks necessary to identify the demodulated signal as a valid MLS transmission.

Brief Description of the Drawings

Figures 1 - 3 illustrate the Microwave Landing System (MLS) Signal Formats.

Figure 4 illustrates the organization of the MLS function preamble.

Figure 5 illustrates the detection principle in Differential Phase Shift Keying (DPSK) decoding.

Figure 6 illustrates one prior art technique of MLS DPSK demodulation.

Figure 7 illustrates one embodiment of the present invention.

Figure 8 illustrates phasor diagrams for various stages in demodulation process.

Figure 9 illustrates typical MLS receiver architecture.

Figure 10 illustrates a system for developing in-phase and quadrature components of a complex baseband envelope.

Figure 11 illustrates a pulse width discriminator.

Figure 12 illustrates a Barker Code template.

Figure 13 illustrates a sub-optimum method for Barker Code synchronization.

Figure 14 illustrates a perfect MLS signal.

Figure 15 illustrates a preferred embodiment of the present invention.

Figure 16 illustrates a generalized embodiment of the present invention.

Detailed Description of the Invention

The present invention performs a series of steps which allow for the accurate detection, demodulation, and decoding of DPSK-encoded digital data transmitted as part of the MLS signal format. These functions are performed within a digital signal processor, which, for the purposes of this discussion, may be considered to be a high speed microprocessor.

The theoretical basis of the present invention is based on the following quantitative signal analysis of the MLS signal. The down-converted IF signal at the input to the A/D converter illustrated in Figure 7 may be represented by: (1)   s(t) = x(t) Real[exp{-j(wt+ Φ(t))}]

where:

   x(t) is the MLS amplitude modulation due to either the scanning beam or the pattern of the antenna used to transmit the preamble information. During DPSK transmissions, we can assume x(t) = V = (a constant);

   w is the radian frequency of the IF signal, including inaccuracies in the ground and airborne systems, i.e.; (1a) w = wif + εif

   Φ(t) is the DPSK information phase. Φ(T) is either 0 or π radians.

It is well known that s(t) can also be expressed in rectangular form in terms of the in-phase and quadrature components sI(t) and sQ(t). (2)   s(t) = Real[sI(t)+jsQ(t)]

In Differential Phase Shift Keying (DPSK) of digital information, the information is conveyed by the presence or absence of a π radian (180°) difference in carrier phase between consecutive bit periods. In the MLS application, a binary 1 is indicated by a phase difference of π radians, while a binary 0 is indicated by no phase change.

Classical DPSK demodulation requires that the input signal s(t) be delayed by a time equal to the reciprocal of the data rate (T = l/Fd) and then used as a reference signal in a mixer. In polar form:

where the "*" indicates the operation of a complex conjugation. Since in DPSK, the phase difference between two signals separated by T will be either 0 or π radians, depending on the binary information, v(t) is a binary phase shift keyed (BPSK) video waveform. We will define ΦI(t) as the information phase. (3a)   ΦI(t) = Φ(t) - Φ(t-T)

Equation (3) indicates the two primary problems with this simple approach to DPSK demodulation for MLS applications. First of all, equation (3) indicates that there are values of wT for which the video signal v(t) is zero everywhere, and therefore no information can be decoded. Second, if w is unknown, as is the case in MLS applications, there is no way to identify the ΦI(t) = π and ΦI(t) = 0 states.

One solution to the first problem is to process v(t) as a complex value, as follows.

In this case, both the real and imaginary parts of vc(t) contain the BPSK information, which can therefore always be decoded. This approach does not solve the problem of an unknown IF frequency, w, however.

When the frequency w is precisely known, equation (3) completes the DPSK demodulation process, since, with wT known, we can interpret a priori whether positive values of v(t) correspond to an information bit of 1 or 0. As mentioned in the description of the prior art, however, frequency drifts in the ground and airborne MLS systems and doppler shifts due to aircraft motion can combine to cause wT to vary by more than 2π radians. Thus, in MLS applications, we can never know the frequency w with sufficient accuracy to allow a priori interpretation of the information states.

The MLS signal format illustrated in Figure 4 provides a means to overcome this difficulty by using the carrier acquisition period at the beginning of each MLS preamble. During this period, the C-band MLS carrier, and thus the IF output signal s(t), contains no phase modulation. In terms of equations (3)and (3a), (5)   ΦI(t) = Φ(t) - Φ(t-T) = 0

during the carrier acquisition period, thus corresponding to a string of DPSK zeros. If we form an estimate of the complex signal during this time using equations (4) and (5).

Under the assumption that the effective IF frequency, w, does not change significantly over the DPSK message, the value of r(t) at the end of the carrier acquisition period can then be used as a complex reference signal to correct the vc(t) value derived from equation (4) for the unknown effective IF frequency, w, through a simple rotation. This simplifying assumption is valid in MLS operations, thus:

The real part of b(t) is

which is a normal BPSK video signal with a value of +V&sup4; for binary information of 0 and -V&sup4; for binary information of 1.

One of the advantages of the present invention is the removal of the effects of the unknown rotation wT. This is achieved by the application of the complex phase correction/rotation factor, r(t), after the DPSK demodulation process indicated by equation (3). As discussed earlier, previous implementations have always corrected for unknown IF phase and frequency errors before the DPSK demodulation.

A block diagram for one embodiment of the DPSK demodulation and decoding technique is illustrated in Figure 7. IF signals having phase pulses of length T enter bandpass filter 11. Samples of the band-limited, down-converted MLS waveform are taken through A/D converter 12 into digital signal processor 13. Within digital signal processor 13, these samples are decomposed in Rader processor 14 into in-phase and quadrature components. The algorithms utilized in Rader processor 14 are discussed in "A Simple Method for Sampling In-Phase and Quadrature Components", Rader, C.M., IEEE Transactions on Aerospace and Electronic Systems, Vol. AES-20, No. 6, November 1984, as disclosed earlier. These components are treated as a single sample of the complex baseband envelope of the received MLS waveform.

The series of complex samples is delayed by one bit delay 15 for exactly one DPSK bit time and flows through the complex conjugate operation 16. The coherent detector 17 with its complex multiplier 18 and its sliding window average 19 takes the complex conjugate of the delayed sequence and multiplies it by the undelayed sequence. The signal is then low pass filtered by averaging together all samples in the previous bit period. This averaging process is known as the sliding window average. This series of operations results in a sequence of complex values whose phase angles are a measure of the phase difference between two consecutive DPSK bits.

Due to the fundamental uncertanties in the MLS IF frequency, the resultant series of complex values may have any phase angle. All values corresponding to consecutive bits which are in-phase will have nearly the same angle Φ&sub1;. All values corresponding to consecutive bits which are out of phase will likewise have a common value Φ&sub2;, where Φ&sub1; - Φ&sub2; = 180°.

The series of complex values out of coherent detector 17 then enters a phase reference calculator 20 where the values are filtered through a low-pass filter 21 to smooth effects of measurement noise. During the 13 bit carrier acquisition period of each MLS preamble, the complex output of low pass filter 21 establishes a "reference" estimate, r(t), which explicitly defines the in-phase angle of Φ&sub1;. The complex output then enters the complex conjugate 22 and the complex conjugate of the low pass filter output, r*(t), enters the reference latch 23. The latched value is used as a reference vector for the phase corrector 24 which includes a phase correction complex multiplier 25 which rotates the phase detector output onto the real axis. Following this rotation, as shown in Figure 8, all binary 0 values 35 will lie on or very near to the positive real axis 36, while all binary 1 values 35 will lie on or very near to the negative real axis 37. Since the result of the complex multiplier 25 is on, or very near, the real axis, only the real part need be used for further processing.

Figure 8a illustrates the input signal, s(t) 31, in polar form as a rotating vector of length V and angular frequency w. The complex output of the coherent detector, Vc(t) 32 is shown in Figure 8b as either of two fixed vectors with magnitude V² and fixed phase of either wT or wT + π, depending on the encoded information. Note that vc(t) 32 is no longer rotating. As illustrated in Figure 8c, the reference signal, r(t) 33, is established during the 832 usec period of unmodulated carrier, therefore it has a phase angle of wT. Its conjugate r*(t) is also illustrated. Finally, Figure 8d illustrates the result of using r*(t) to correct vc(t). When the information is a binary zero, bc(t) 35 lies on or near the positive real axis 36. When the information is a binary 1, bc(t) 35 lies on or near the negative real axis 37.

Note that the actual phase of the complex signal is never computed directly. All of the processing from the Rader decomposition through the carrier tracking filter is performed on the complex values and therefore requires only multiplication and addition operations which can be performed at high speed in a microcomputer or in dedicated arithmetic hardware. There are no divisions or inverse trigonometric functions to be computed, thereby allowing the technique to be applied to higher data rates.

Returning to Figure 7, the real result of the final phase rotation of the phase corrector 24 is applied to a pulse width discriminator 27, which is set to identify the presence of the 13-bit carrier acquisition signal. When the presence of this carrier acquisition signal is detected, the reference signal, r(t), is fixed for the duration of the MLS transmission.

Following the pulse width function discriminator 27 the real result flows through a data sync 28 which applies algorithms to detect the characteristic Barker code and establish bit synchronization. The result than flows through a data sample 29 which applies algorithms which sample the result to establish binary information in accordance with the signal format and parity constraints defined in Annex 10 to the Convention on International Civil Aviation; Volume 1, Chapter 3.11, ICAO, Montreal, October 1987.

To further describe the input signal, we can utilize typical MLS receiver architecture as illustrated in Figure 9, where the C-band MLS signal, including data and scanning beam transmissions, is down-converted and amplified from the 5 GHz range to a convenient IF frequency. In the process, a single MLS channel is selected by filtering the IF signal through a bandpass filter. The bandwidth of this filter is chosen to allow for worst case combinations of ground frequency drift, aircraft doppler, and MLS receiver local oscillator drift. The shape of this filter is chosen to accommodate the 300 kHz channel spacing required in Annex 10 to the Convention on International Civil Aviation; Volume 1, Chapter 3.11, ICAO, Montreal, October 1987 and the adjacent channel rejection requirements stated in Minimum Operational Performance Standards for Microwave Landing System Airborne Receiving Epuipment, DO-177, Change 2, RTCA, Washington, D.C., September 1986. The effect of this filter is to band-limit the MLS signal. Typical MLS receiver designs have chosen multiple pole filters with an IF bandwidth of 100-150 kHz to satisfy these requirements.

It is important to note that the requirements on MLS receiver bandwidth are primarily driven by frequency source stability and not the actual information bandwidth of the MLS signal, which is approximately equal to the DPSK data rate, 15.625 kHz.

When the input signal enters the digital signal processor 13 of Figure 7, it is processed by Rader processor 14. "A Simple Method for Sampling In-Phase and Quadrature Components", Rader, C.M., IEEE Transactions on Aerospace and Electronic Systems, Vol AES-20, No. 6, November 1984 describes a technique for decomposing an IF signal into its constituent in-phase (I) and quadrature (Q) components using a combination of a rapid sample rate, relatively low IF frequency, and digital filtering techniques. As described by Rader, if the total bandwidth of the signal is B Hertz, the desired IF frequency is B Hertz, and the desired sample rate is 4B samples per second. The output of the Rader processor 13 is a stream of I and Q samples, each occurring at a rate B, describing the complex baseband envelope of the IF waveform. Figure 10 illustrates an implementation of the Rader technique. As is illustrated in Figure 10, the IF signal enters bandpass filter 41 and then flows to A/D converter 42. The signal then enters Rader processor 43 where the IF signal is decomposed into its in-phase (I) 44 and quadrature (Q) 45 components.

Applying the Rader processor 43 to a signal band-limited by an MLS IF filter described in the previous paragraph would indicate a sample rate of 400-600 kHz (2.5 - 1.66 usec spacing), and a minimum IF frequency of 100-150 kHz. These sample rates and IF frequencies result in a near-perfect representation of the complex baseband envelope of the entire 100-150 kHz MLS bandwidth, which as noted earlier, is six to ten times greater than the information bandwidth of the MLS DPSK channel.

The Rader processor 43 relies on the 4:1 relationship of the input and output sample rates to simplify the implementation of filters H&sub1;(z) 46 and H&sub2;(z) 47. The technique works with virtually no degradation even when the actual sample rate and IF frequency vary slightly from the 4:1 relationship. For the purposes of demodulating the MLS DPSK, it is extremely desirable to have an integer number of samples occur in a single DPSK bit period of 64 usec. Thus, a preferred sample rate is 500 kHz providing 2 usec sample spacing and 32 samples per DPSK bit. A sample rate of 250 kHz or below is unacceptable, since it will lead to aliasing of the IF frequency and will disrupt the I and Q relationship of the Rader processor 43 outputs.

A key feature of the Rader processor 43 is that the net filter transfer function H(z) is complex, consisting of H&sub1;(z) + jH&sub2;(z). Thus the H(z) filter is unrealizable in a physical sense without decomposition into I and Q channels via a power divider, quadrature mixers, etc. This approach of processing the complex envelope of the signal is carried throughout the remaining DPSK demodulation process.

Following the Rader processor decomposition, we are left with I and Q samples spaced 8 usec apart. In the event that the mathematical operations described next can not be accomplished in this period, acceptable performance may be obtained by further down-sampling this complex envelope to 16 usec, 32 usec or even 64 usec intervals. The minimum sample rate of 15,625 complex samples per second still satisfies all Nyquist requirements for the 15.625 kHz MLS bit rate. Such down-sampling may cause aliasing of any error frequency ε and will reduce noise performance by eliminating the possibility for filtering the phase detector output. Aliasing of the error frequency ε will not, in itself, affect the succeeding processing.

The coherent detection process of the coherent detector 17 of Figure 7 involves a straightforward complex multiplication in rectangular form. This process involves only multiplication and addition operations, and can thus be efficiently implemented in either hardware or software. With a complex input signal s(t) from the Rader processor 14 we have the following. (9)   s(t)= sI(t) + jsQ(t)

The coherent detector output is this result filtered by the sliding window average 19 having a duration equal to the DPSK bit width of 64 usec. Assuming the nominal 8 usec period between samples (τ = 8 usec), there are eight samples within the sliding window.

This filtering process requires only additions and a 3 place binary shift to divide by eight.

The phase reference computation as performed by the phase reference 20 will now be described. During the 13 bit carrier acquisition period, the complex synchonous detector output vc(t) given by equation (11) is essentially constant. This complex value is first low pass filtered by low pass filter 21 to establish the reference phase signal r(t). Although the filter implementation is up to the designer, a single pole recursive filter has demonstrated adequate performance. (12)   r(t) = Ar(t-τ) + (1-A)vc(t)

where τ is the net sample rate, nominally 8 usec.

The signal then flows to the phase corrector 24 where the complex value r(t) is used as an estimate of the unknown "zero-degree phase" vector, including any effects of IF frequency errors. A corrected signal bR(t) is created in accordance with equation (8), using the rectangular form of r(t). (13)   bR(t) = vcI(t)rI(t) + VcQ(t)rQ(t)

Once again, this process is implemented in either hardware or software with only a simple multiply and accumulate function. Some intermediate scaling of the multiplicands may be necessary to prevent overflow of the result bR(t).

The real output bR(t) is an integer value whose algebraic sign represents the encoded binary information. After the Rader processor 14, sliding window average 19, and low pass filters 21 have settled down, this value will remain positive for the remainder of the 13 bit acquisition period. The pulse width discriminator 27 checks the sign of bR(t), and enables further processing when the signal is positive for longer than a fixed period of time. In the preferred MLS embodiment, this period is set to 640 usec, or 10 DPSK bits.

The pulse width discriminator 27 involves a digital comparator 51 and a binary down counter 52, as shown in Figure 11, and can be implemented in either hardware or software, as appropriate to the intended application.

The output of the pulse width discriminator 27 is low until a valid pulsewidth is detected. Upon detection the output transitions immediately to a high condition, and remains high until reset at the end of the MLS function. The low-to-high transition causes two actions to occur:

  • (1) the complex reference value r(tpwd) at the transition time, tpwd, is latched and used for the remainder of the DPSK function;
  • (2) the real BPSK video output, consisting of a sequence of digital words representing bR(t) is gated to the synchronization and data sampling algorithms, discussed below.

The data sync 28 will now be described. The MLS signal format utilizes a five bit Barker Code (binary data 11101) for receiver time synchronization. This code is transmitted immediately following the 13 bit acquisition period. The receiver reference time is defined as the midpoint of the final phase transition.

This reference time is ideally recovered by use of a matched filter to correlate the received BPSK video signal bR(t) against a Barker Code template, BC(t). To ensure proper operation, BC(t) must be sampled at the same rate as bR(t), thus, for the 8 usec sample rate used in this discussion, the Barker Code Template, BC is shown in Figure 12. Use of a matched filter approach will result in the best approximation of the true reference time.

Time constraints on the real time processing may make the ideal matched filter impractical to implement. Sub-optimal methods of attaining synchronization are acceptable in the MLS application. One such technique which has been shown to provide acceptable MLS performance is the "zero-crossing-reset" method which is illustrated in Figure 13, and discussed below..

Once the pulse width discriminator 27 of Figure 7 has indicated that a valid candidate signal is present, successive values of bR(t) are examined until the first sign crossing takes place. In a perfect MLS signal, as illustrated in Figure 14, this should occur at the end of the 13th acquisition bit, which is a logical "0" and the start of the first Barker Code "1". If there are N samples per DPSK bit (N=8 for 8 usec samples), the sign of the (N/2)th value of bR(t) after the sign transition is examined, and the appropriate BPSK binary value ("0" or "1") is entered into a five bit shift register. This process is repeated every Nth sample after this first entry until either another sign change is-detected or ten bits are sampled.

If another sign change is detected between samples of the BPSK binary value, the succeeding BPSK sample is taken (N/2) samples after the transition, this process is repeated every Nth sample after the new BPSK sample until either another sign change is detected or a total of ten bits are sampled.

As each new BPSK sample is shifted into the shift register, the register contents are compared to the Barker Code template of 11101. If a Barker Code match occurs, the interpolated zero crossing between the two samples bracketing the previous sign changes is accepted as the reference time. This interpolation process may require a microprocessor, although all other steps are effectively implemented directly in hardware.

If no Barker Code match occurs after 10 BPSK data samples, the entire demodulation process, including the pulse width discriminator and all filter memories, is reset and restarted.

The data sampling process performed in data sample 29 of Figure 7 is described as follows. Once the Barker Code has been identified, the sign of every Nth BPSK video value is examined to arrive at the proper BPSK data. Positive BPSK video values are logical BPSK "0" values. Negative BPSK video values are logical BPSK "1" values. At this point, conventional data decoding, parity checking and data validation algorithms may be used.

A block diagram of a preferred embodiment of the present invention is illustrated in Figure 15. In this embodiment, the high-speed capabilities of the TMS-320C25 digital signal processor chip 61 with its ROM 62, RAM 63 and oscillator 64 are utilized to implement the entire process just described in software. Support logic includes a 12-bit analog-to-digital converter 65 and its associated timing and control circuitry 66. The interface to the digital signal processor chip 61 is through a FIFO 67. The counter 68 is used to count a fixed number of data samples (either 4 or 8) collected in the FIFO 67 before digital signal processor interrupt request are issued.

A block diagram of a more generalized embodiment of the present invention is shown in Figure 16. This embodiment is based on the same general purpose hardware-digital signal processor architecture illustrated in U.S. Patent No. 4,926,186 by Kelly and LaBerge and assigned to the same assignee as the present invention. This architecture uses one of several commercially available multiply and accumulator (MAC) chips 71 under microcode control from the microcoded controller 72 to perform the various arithmetic operations described earlier at a significantly higher speed than that currently available in a software controlled digital signal processor chip. Also illustrated in Figure 16 is microprocessor 73, pulse width discriminator 74, sample counter 75 and A/D Converter 76 with its timing and control circuitry 77. Increasing the computation speed, allows use of a higher A/D clock rate and correspondingly higher IF frequency and signal bandwidth. This implementation may be attractive when adopting the present invention to non-MLS applications.

Although the present invention was developed specifically for an MLS application, it may be applicable to any DPSK demodulation application, providing an MLS-like carrier acquisition period is available.

It is not intended that this invention be limited to the hardware or software arrangement, or operational procedures shown disclosed. This invention includes all of the alterations and variations thereto as encompassed within the scope of the claims as follows.


Anspruch[de]
  1. System zur Demodulierung und zur Decodierung von Sendungen die durch Modulation differentielle Modulation des Phasenversatzes codiert sind, das eine Bandpass - Filterstufe (11) enthält, um analoge Signale zu empfangen, und um gefilterte analoge Signale einer Vorrichtung zur Signalverarbeitung (12-13, 42-43, 65-61, 76-73) zuzuführen, wobei die erwähnte Vorrichtung zur Signalverarbeitung Information erzeugt, die demodulierte und decodierte Sendungen, die durch differentielle Modulation des Phasenversatzes codiert sind, darstellt, und Fähigkeiten zur Verfolgung und zur Korrektur der Phase aufweist, dadurch gekennzeichnet, dass die erwähnte Vorrichtung zur Signalverarbeitung eine Vorrichtung zur Umsetzung von Analog zu Digital (12, 42, 65, 76) enthält, die die erwähnten gefilterten analogen Signale empfängt, und eine Vorrichtung zur digitalen Signalverarbeitung (13, 43, 61, 73), die die digitalen Signale von der erwähnten Vorrichtung zur Umsetzung von Analog zu Digital (12, 42, 65, 76) empfängt, und zur Umsetzung der erwähnten digitalen Signale in komplexe Signale von Komponenten, die in Phase und in Quadratur stehen, mittels digitaler Mittel, zur Bereitstellung von Detektierung der Kohärenz der erwähnten komplexen Signale von Komponenten, die in Phase und in Quadratur sind, wodurch komplexe detektierte Signale bereitgestellt werden, um danach die Verfolgung der Phase vor der Demodulierung und die Korrektur der Phase von jedem Phasenfehler von dem erwähnten komplexen Signal nach der Demodulierung vorzusehen, und zur angemessenen Decodierung von DPSK - modulierter Information des Mikrowellen gestützten gestützten Landesystems MLS; wobei die erwähnte Vorrichtung zur digitalen Signalverarbeitung (13, 43, 61, 73) folgendes beinhaltet:

       eine Vorrichtung zur Signalverarbeitung nach Rader (14) die die erwähnten digitalen Signale empfängt und die die erwähnten digitalen Signale in die erwähnte Folge von komplexen Signalen von Komponenten auflöst, die in Phase und in Quadratur sind;

       eine Vorrichtung zur Verzögerung (15) die die erwähnte Folge von komplexen Signalen verzögert;

       eine Vorrichtung zum Konjugieren (16) um die erwähnten verzögerten Folgen von Signalen zu empfangen und deren Konjugierte zur Verfügung zu stellen;

       eine Vorrichtung zur Detektierung der Kohärenz (17) um die erwähnte Konjugierte der erwähnten Folge von komplexen Signalen zu empfangen und um ebenso eine nicht verzögerte Folge direkt von der erwähnten Vorrichtung zur Signalverarbeitung nach Rader (14) zu empfangen und um eine demodulierte Folge von komplexen Werten zur Verfügung zu stellen, deren Phasenwinkel ein Mass des Phasenunterschiedes zwischen zwei einander folgenden mittels differentieller Modulation des Phasenversatzes codierter Bits ist;

       eine Vorrichtung für die Bezugsphase (21, 22, 23) um die erwähnte demodulierte Folge von komplexen Werten aus der erwähnten Vorrichtung zur Detektierung der Kohärenz (17) zu filtern, und daher einen Bezugs - Schätzwert von r(t) herzustellen, um den erwähnten Bezugs - Schätzwert r(t) komplex zu konjigieren, und daher eine komplex Konjugierte zur Verfügung zu stellen, um die erwähnte komplex - Konjugierte zu speichern, und um einen gespeicherten Wert zur Verfügung zu stellen, der als Bezugs - Vektor verwendet wird;

       eine Vorrichtung zur Korrektur der Phase (25) die den erwähnten gespeicherten Wert empfängt, und auch die erwähnte demodulierte Folge von komplexen Werten direkt von der erwähnten Vorrichtung zur Detektierung der Kohärenz (17) und die die erwähnte demodulierte Folge von komplexen Werten auf die Reale Achse dreht, und daher ein reales Resultat zur Verfügung stellt;

       eine Vorrichtung zum Diskriminieren der Pulsbreite (27) um das erwähnte reale Resultat von der erwähnten Vorrichtung zur Korrektur der Phase (25) zu empfangen, um das Vorliegen eines Trägerfrequenz - Eingabesignals von 13 Bit zu erkennen, um ein Bezugssignal r(t) für die Dauer der Sendung des Systems zu fixieren, und um ein Signal zur Verfügnug zu stellen, das die Detektierung einer gültigen Pulsbreite anzeigt;

       eine Vorrichtung zum Synchronisieren der Daten (28) um das erwähnte reale Resultat der erwähnten Vorrichtung zum Korrigieren der Phase (25) und das erwähnte Signal, das die Detektierung einer gültigen Pulsbreite anzeigt, von der erwähnten Vorrichtung zum Diskriminieren der Pulsbreite (27) zu empfangen, um Algorithmen anzuwenden, um einen characteristischen Barker - Code zu detektieren, und um eine Bit - Synchronisation vorzusehen, und um ein Ausgangssignal vorzusehen; und

       eine Vorrichtung zum Abtasten der Daten (29) um das erwähnte Ausgangssignal von der erwähnten Vorrichtung zum Synchronisieren der Daten (28) zu empfangen, um Algorithmen anzuwenden die das erwähnte Ausgangssignal abtasten, um binäre Ausgabe - Information zu erstellen, die demodulierte und decodierte, durch differentiell modulierten Phasenversatz codierte Sendungen darstellt.
  2. Ein System wie in Anspruch 1 beschrieben, wobei die erwähnte Vorrichtung zum Bandpass - Filtern (11) gefilterte analoge Signale zur Verfügung stellt, die Abtastungen einer in seiner Bandbreite begrenzten, heruntergemischten Wellenfrom eines Mikrowellen gestützten Landungssystems sind.
  3. System wie in Anspruch 1 beschrieben, wobei die erwähnte Vorrichtung zur Signalverarbeitung nach Rader (14) die erwähnten digitalen Signale in eine Folge von komplexen Signalen von Komponenten, die in Phase sind und solchen die in Quadratur sind, auflöst, und die als einzelne Abtastung einer komplexen Basisband - Einhüllenden der empfangenen Wellenform behandelt werden.
  4. System zur Demodulation und Decodierung von durch differentiell modulierten Phasenversatz codierten Sendungen wie in Anspruch 1 beschrieben, wobei darüber hinaus enthalten sind:

       die erwähnte Vorrichtung zur digitalen Signalverarbeitung (13, 43, 61, 73) um die erwähnten digitalen Signale zu empfangen, und um demodulierte und decodierte mit der Winkel Funktion zusammenhängende in durch differentiell modulierten Phasenversatz codierte Sendungen, wobei die tatsächliche Phase einer Folge von komplexen Signalen nie direkt errechnet wird, und alle Schritte der Verarbeitung, beginnend von der Zerlegung nach Rader bis zum Filter zur Verfolgung der Trägerfrequenz an der erwähnten Folge von komplexen Signalen ausgeführt wird, und wo daher die Verarbeitung nur Operationen der Multiplikation und der Addition erfordern, und die Korrektur jedes Fehlers der Phase nach der Demodulation erfolgt.
  5. System zur Demodulation und Decodierung von durch differentiell modulierten Phasenversatz codierten Sendungen wie in Anspruch 1 beschrieben, wobei darüber hinaus enthalten sind:

       die erwähnte Vorrichtung zum Umsetzen von Analog zu Digital (65), die IF Signale des Mikrowellen - Lande - Systems empfängt, und die digitale Daten ausgibt, sowie ein Signal, das die Bereitschaft der Daten anzeigt;

       eine FIFO Vorrichtung (67) um die erwähnten digitalen Daten von der erwähnten Vorrichtung zum Umsetzen von Analog zu Digital (65) zu empfangen, und um FIFO Ausgangsdaten zur Verfügung zu stellen;

       eine Vorrichtung zum Zählen (68) der Abtastungen die das erwähnte Signal, das die Bereitschaft von Daten anzeigt, von der erwähnten Vorrichtung zum Umsetzen von Analog zu Digital (65) empfängt, und ein Unterbrechungs - Signal für die Datenbereitschaft zur Verfügung stellt;

       eine Vorrichtung zur digitalen Signalverarbeitung (61) um die erwähnten FIFO Ausgangsdaten und das erwähnte Unterbrechungs - Signal für die Datenbereitschaft zu empfangen, und die Takt Signale zur Verfügung stellt sowie demodulierte und decodierte Signale von durch differentielle Modulation des Phasenversatzes codierten Sendungen zur Verfügung stellt, wobei die Korrektur des Fehlers der Phase nach der Demodulation vorgenommen wird;

       eine Schwingkreis - Vorrichtung (64) um die Takt Signale für die erwähnte Vorrichtung zur digitalen Signalverarbeitung (61) zur Verfügung zu stellen;

       eine Vorrichtung zum Speichern (62, 63) um Speicherplatz zur Berechnung zur Verfügung zu stellen, die von der erwähnten Vorrichtung zur digitalen Signalverarbeitung (61) ausgeführt wird; und

       Vorrichtungen zur Steuerung und zur Generierung des Takts für die Umsetzung von Analog zu Digital (66) die Takt Information und Signale von der erwähnten Vorrichtung zur digitalen Signalverarbeitung (61) empfängt, und Takt und Steuerung für den erwähnten Umsetzer Analog zu Digital (65) zur Verfügung stellt.
  6. Verfahren zum Demodulieren und zum Decodieren von Sendungen, die durch differentielle Modulation des Phasenversatzes codiert sind, das die folgenden Schritte aufweist:

       Filterung der empfangenen Signale zu gefilterten Signalen;

       Verarbeitung der erwähnten gefilterten Signale samt Verfolgung deren Phase und Korrektur der Phase, um Information zu erzeugen, die demodulierte und decodierte Sendungen, die durch differentielle Modulation des Phasenversatzes codiert wurden, darstellt;

    dadurch gekennzeichnet das der erwähnte Schritt der Verarbeitung die folgenden Schritte enthält:

       der Umwandlung der erwähnten gefilterten Signale zu digitalen Signalen; und

       der digitalen Verarbeitung der erwähnten digitalen Signale um die erwähnten digitalen Signale durch digitale Mittel zu komplexen Signalen von Komponenten in Phase und in Quadratur aufzulösen, um Detektion der Kohärenz der erwähnten komplexen Signale von Komponenten in Phase und in Quadratur vorzusehen, was zu komplexen, detektierten Signalen führt, um anschliessend die Verfolgung der Phase vor der Demodulation und die Korrektur der Phase betreffend jeden Fehler der Phase von den erwähnten komplexen Signalen vorzunehmen, und um die DPSK - Information des Mikrowellen gestützten Lande - Systems ordentlich zu decodieren; wobei der erwähnte Schritt der digitalen Verarbeitung die folgenden Schritte enthält:

       des Empfangens der erwähnten digitalen Signale in einer Vorrichtung zur.Verarbeitung nach Rader (14) und der Auflösung der erwähnten digitalen Signale zu einer Folge von komplexen Signalen von Komponenten in Phase und in Quadratur durch digitale Mittel;

       der Verzögerung der erwähnten Folge von komplexen Signalen;

       dem Bereistellen einer Konjugierten der erwähnten verzögerten Folge von komplexen Signalen;

       dem Empfang der erwähnten Konjugierten der erwähnten verzögerten Folge von komplexen Signalen in einer Vorrichtung zum Detektieren der Kohärenz (17), die ebenso eine nicht verzögerte Folge direkt von der erwähnten Vorrichtung zur Verarbeitung nach Rader (14) empfängt, und eine demodulierte Folge von komplexen Werten zur Verfügung stellt, deren Phasenwerte ein Mass für die Phasenunterschiede zwischen zwei, einander folgenden, durch differentielle Modulation des Phasenversatzes codierten Bits ist;

       der Filterung in den Vorrichtungen zur Bereitstellung der Bezugsphase (21, 22, 23) der erwähnten Folge von komplexen Werten von der erwähnten Vorrichtung zur Detektierung der Kohärenz (17), wobei daher eine Schätzung des Bezugssignals r(t) hergestellt wird, die erwähnte Schätzung des Bezugssignals r(t) komplex konjugiert wird, wobei eine komplex Konjugierte zur Verfügung gestellt wird, die erwähnte komplex Konjugierte gespeichert wird, und ein fest gespeicherter Wert zur Verfügung gestellt wird, der als Referenz - Vektor verwendet wird;

       dem Empfang des erwähnten gespeicherten Wertes in einer Vorrichtung zur Korrektur der Phase (25) und der erwähnten demodulierten Folge von komplexen Werten direkt von der erwähnten Vorrichtung zur Detektion der Kohärenz (17), und zum Drehen der erwähnten demodulierten Folge von komplexen Werten auf die real Achse, wobei ein reales Resultat zur Verfügung gestellt wird;

       dem Empfang des erwähnten realen Resultats durch Vorrichtungen zur Diskriminierung der Pulsbreite (27), wobei das erwähnte Resultat aus der erwähnten Vorrichtung zur Korrektur der Phase (25) das Vorliegen eines 13 Bit langen Einlesesignals der Trägerfrequenz anzeigt, das Bezugssignal r(t) für die Dauer der Sendezeit des Systems fixiert wird, und ein Detektionssignal für eine korrekte Pulsbreite zur Verfügung gestellt wird;

       dem Empfang des erwähnten realen Resultats von der erwähnten Vorrichtung zur Korrektur der Phase (25) in einer Vorrichtung zur Synchronisierung der Daten (28) sowie auch des erwähnten Detektionssignals für eine korrekte Pulsbreite aus der erwähnten Vorrichtung zur Diskriminierung der Pulsbreite (27), der Anwendung von Algorithmen um einen charkteristischen Barker Code zu erkennen, und der Errichtung einer Bit - Synchronisation um ein Ausgangssignal zur Verfügung zu stellen; und

       dem Empfang des erwähnten Ausgangssignals von der erwähnten Vorrichtung zur Synchronisierung der Daten (28) in einer Vorrichtung zum Abtasten der Daten (29) und der Anwendung von Algorithmen, die das erwähnte Ausgangssignal abtasten, um eine binäre Ausgabe - Information zu erstellen, die demodulierte und decodierte Information von durch differentielle Modulation des Phasenversatzes codierten Sendungen darstellt.
Anspruch[en]
  1. A system for demodulating and decoding differential phase shift keying transmissions comprising bandpass filter means (11) for receiving analog signals and for providing filtered analog signals to signal processor means (12-13, 42-43, 65-61, 76-73), said signal processor means generating information representing demodulated and decoded differential phase shift keying transmissions and being provided with phase tracking and phase correction capabilities, characterized in that said signal processor means includes analog to digital converter means (12, 42, 65, 76) receiving said filtered analog signals and digital signal processor means (13, 43, 61, 73) for receiving digital signals from said analog to digital converter means (12, 42, 65, 76) and for resolving said digital signals into complex signals of in-phase and quadrature components by digital means, for providing coherent detection of said complex signals of in-phase and quadrature components which provides detected complex signals, for then providing phase tracking before demodulation and phase correction of any phase error of said detected complex signals after demodulation, and for proper decoding of Microwave Landing System DPSK information; said digital signal processor means (13, 43, 61, 73) including:

       Rader processor means (14) which receives said digital signals and resolves said digital signals into a series of complex signals of in-phase and quadrature components by digital means;

       delay means (15) which delays said series of complex signals;

       conjugate means (16) for receiving said delayed series of complex signals and for providing a conjugate;

       coherent detector means (17) for receiving said conjugate of said delayed series of complex signals and also for receiving an undelayed series directly from said Rader processor means (14) and for providing a demodulated series of complex values whose phase angles are a measure of phase difference between two consecutive differential phase shift keying bits;

       phase reference means (21, 22, 23) for filtering said demodulated series of complex values from said coherent detector means (17) therefore establishing a reference estimate of r(t), for complex conjugating said reference estimate of r(t) therefore providing a complex conjugate, for latching said complex conjugate and for providing a latched value which is used as a reference vector;

       phase corrector means (25) which receives said latched value and said demodulated series of complex values directly from said coherent detector means (17) and rotates said demodulated series of complex values onto a real axis therefore providing a real result;

       pulse width discriminator means (27) for receiving said real result from said phase corrector means (25), for identifying presence of a 13-bit carrier acquisition signal, for fixing a reference signal r(t) for duration of system transmission and for providing a valid pulse width detect signal;

       data sync means (28) for receiving said real result from said phase corrector means (25) and said valid pulse width detect signal from said pulse width discriminator means (27), for applying algorithms to detect a characteristic Barker code and establish bit synchronisation and for providing an output signal; and

       data sample means (29) for receiving said output signal from said data sync means (28) and for applying algorithms which sample said output signal to establish binary output information representing demodulated and decoded diferential phase shift keying transmissions.
  2. A system as described in claim 1, wherein said bandpass filter means (11) provides filtered analog signals which are samples of a band-limited down-converted Microwave Landing System waveform.
  3. A system as described in claim 1, wherein said Rader processor means (14) resolves said digital signals into a series of complex signals of in-phase and quadrature components which are treated as a single sample of a complex baseband envelope of a received waveform.
  4. A system for demodulating and decoding differential phase shift keying transmissions as described by claim 1, further including:

       said digital signal processor means (13, 43, 61, 73) for receiving said digital signals and for providing demodulated and decoded angle function related differential phase shift keying transmissions, wherein actual phase of a series of complex signals is never computed directly, all processing from Rader decomposition through carrier tracking filter is performed on said series of complex signals and therefore processing requires only multiplication and addition operations and correction of any phase error occurs after demodulation.
  5. A system for demodulating and decoding differential phase shift keying transmissions as described by claim 1, further including:

       said analog to digital converter means (65) receiving Microwave Landing System IF signals and for outputting digital data and a data ready signal;

       FIFO means (67) for receiving said digital data from said analog to digital converter means (65) and for providing a FIFO output;

       sample counter means (68) which receives said data ready signal from said analog to digital converter means (65) and provides a data ready interrupt signal;

       digital signal processor means (61) for receiving said FIFO output and said data ready interrupt signal and for providing timing signals and demodulated and decoded differential phase shift keying transmissions, wherein phase error correction occurs after demodulation;

       oscillator means (64) for providing processor timing signals to said digital signal processor means (61);

       memory means (62, 63) for providing storage for processing performed by said digital signal processor means (61); and

       analog to digital timing and control means (66) which receives timimg and signals from said digital signal procesor means (61) and provides timing and controlling to said analog to digital converter means (65).
  6. A method for demodulating and decoding differential phase shift keying transmissions comprising the steps of:

       filtering received signals into filtered signals;

       processing said filtered signals including phase tracking and phase correction to generate information representing demodulated and decoded differential phase shift keying transmissions;

    characterized in that said step of processing includes the steps of:

       converting said filtered signals into digital signals; and

       digitally processing said digital signals for resolving said digital signals into complex signals of in-phase and quadrature components by digital means, for providing coherent detection of said complex signals of in-phase and quadrature components which provides detected complex signals, for then providing phase tracking before demodulation and phase correction of any phase error of said detected complex signals, and for proper decoding of Microwave Landing System DPSK information; said step of digitally processing including the steps of:

       receiving said digital signals in Rader processor means (14) and resolving said digital signals into a series of complex signals of in-phase and quadrature components by digital means;

       delaying said series of complex signals;

       providing a conjugate of said delayed series of complex signals;

       receiving in coherent detector means (17) said conjugate of said delayed series of complex signals and also receiving an undelayed series directly from said Rader processor means (14) and providing a demodulated series of complex values whose phase angles are a measure of phase difference between two consecutive differential phase shift keying bits;

       filtering in phase reference means (21, 22, 23) said demodulated series of complex values from said coherent detector means (17) therefore establishing a reference estimate of r(t), complex conjugating said reference estimate of r(t) therefore providing a complex conjugate, latching said complex conjugate and providing a latched value which is used as a reference vector;

       receiving said latched value into phase corrector means (25) and said demodulated series of complex values directly from said coherent detector means (17) and rotating said demodulated series of complex values onto a real axis therefore providing a real result;

       receiving into pulse width discriminator means (27) said real result from said phase corrector means (25), identifying presence of a 13-bit carrier acquisition signal, fixing a reference signal r(t) for duration of system transmission and providing a valid pulse width detect signal;

       receiving into data sync means (28) said real result from said phase corrector means (25) and said valid pulse width detect signal from said pulse width discriminator means (27), applying algorithms to detect a characteristic Barker code and establish bit synchronisation and providing an output signal; and

       receiving into data sample means (29) said output signal from said data sync means (28) and applying algorithms which sample said output signal to establish binary output information representing demodulated and decoded diferential phase shift keying transmissions.
Anspruch[fr]
  1. Système de démodulation et de décodage de transmissions de type à modulation à déphasage différentiel (DPSK) comportant des moyens formant filtre passe-bande (11) pour recevoir des signaux analogiques et pour transmettre des signaux analogiques filtrés à des moyens processeurs de signaux (12-13, 42-43, 65-61, 76-73), lesdits moyens processeurs de signaux générant de l'information représentative de transmissions démodulées et décodées de type à modulation à déphasage différentiel et incorporant des fonctions de recherche de phase et de correction de phase, caractérisé en ce que lesdits moyens processeurs de signaux comportent des moyens convertisseurs analogique/numérique (12, 42, 65, 76) recevant lesdits signaux analogiques filtrés et des moyens processeurs de signaux digitaux (13, 43, 61, 73) pour recevoir lesdits signaux digitaux desdits moyens convertisseurs analogique/numérique (12, 42, 65, 76) et pour décomposer à l'aide de moyens digitaux lesdits signaux digitaux en signaux complexes de composantes en phase et en quadrature et produire des signaux complexes de détection, pour réaliser ensuite une recherche de phase avant démodulation et une correction de phase de toute erreur de phase desdits signaux complexes de détection après démodulation, et pour décoder de façon appropriée de l'information de type DPSK d'un Système d'Atterrissage à Micro-ondes (MLS); lesdits moyens processeurs de signaux digitaux (13, 43, 61, 73) comportant:

       des moyens processeurs de Rader (14) recevant lesdits signaux digitaux et décomposant lesdits signaux digitaux en une série de signaux complexes de composantes en phase et en quadrature à l'aide de moyens digitaux;

       des moyens de temporisation (15) introduisant un retard dans ladite série de signaux complexes;

       des moyens de conjugaison (16) recevant ladite série retardée de signaux complexes pour en obtenir la série conjuguée;

       des moyens de détection de cohérence (17) recevant ladite série conjuguée de ladite série retardée de signaux complexes et recevant également une série non retardée directement desdits moyens processeurs de Rader (14) pour générer une série démodulée de valeurs complexes dont les angles de phase représentent la mesure de la différence de phase entre deux bits consécutifs encodés par déphasage différentiel (DPSK);

       des moyens de référence de phase (21, 22, 23) pour filtrer ladite série démodulée de valeurs complexes à partir desdits moyens de détection de cohérence (17) et établir ainsi une évaluation de référence de r(t), pour réaliser la conjugaison complexe de ladite évaluation de référence de r(t) de façon à générer un conjugué complexe, pour verrouiller ledit conjugué complexe et pour générer une valeur verrouillée qui est utilisée en tant que vecteur de référence;

       des moyens de correction de phase (25) recevant ladite valeur verrouillée et ladite série démodulée de valeurs complexes directement desdits moyens de détection de cohérence (17) et réalisant une rotation de ladite série de valeurs complexes sur l'axe des réels pour obtenir un résultat réel;

       des moyens discriminateurs (27) de durée d'impulsion pour recevoir ledit résultat réel desdits moyens de correction de phase (25), pour identifier la présence d'un signal d'acquisition de porteuse de 13 bits, pour fixer un signal de référence r(t) pour la durée d'une transmission par le système et pour générer un signal de détection de durée d'impulsion valide;

       des moyens de synchronisation de données (28) pour recevoir ledit résultat réel à partir desdits moyens de correction de phase (25) et ledit signal de détection de durée d'impulsion valide à partir desdits moyens discriminateurs (27) de durée d'impulsion, pour mettre en oeuvre des algorithmes de détection d'un code de Barker caractéristique et établir une synchronisation des bits, et pour générer un signal de sortie; et

       des moyens d'échantillonnage de données (29) pour recevoir ledit signal de sortie à partir desdits moyens de synchronisation de données (28) et pour mettre en oeuvre des algorithmes d'échantillonnage dudit signal de sortie pour générer de l'information binaire de sortie représentative de transmissions démodulées et décodées de type à modulation à déphasage différentiel (DPSK).
  2. Système selon la revendication 1, dans lequel lesdits moyens formant filtre passe-bande (11) génèrent des signaux analogiques filtrés qui sont des échantillons d'une onde MLS (Système d'Atterrissage à Micro-ondes) à bande limitée en largeur et après réduction-conversion de fréquence.
  3. Système selon la revendication 1, dans lequel les moyens processeurs de Rader (14) décomposent lesdits signaux digitaux en une série de signaux complexes de composantes en phase et en quadrature qui sont traitées comme un échantillon unique d'une enveloppe complexe de la bande de base d'une onde reçue.
  4. Système de démodulation et de décodage de transmissions de type à modulation à déphasage différentiel (DPSK) selon la revendication 1, comportant de plus:

       des moyens processeurs de signaux digitaux (13, 43, 61, 73) recevant lesdits signaux digitaux pour générer des transmissions démodulées et décodées de type à modulation à déphasage différentiel en fonction de l'angle de phase et dans lesquels la phase exacte d'une série de signaux complexes n'est jamais calculée directement, tout le traitement à partir de la décomposition dans le processeur de Rader jusqu'au filtre de recherche de la porteuse étant réalisé sur ladite série de signaux complexes de telle sorte que le traitement ne nécessite que des opérations de multiplication et d'addition, la correction de l'erreur de phase étant réalisée après la démodulation.
  5. Système de démodulation et de décodage de transmissions de type à modulation à déphasage différentiel selon la revendication 1, comportant de plus:

       des moyens convertisseurs (65) analogique/numérique recevant des signaux de fréquence intermédiaire (FI) de Système d'Atterrissage à Micro-ondes (MLS) pour générer en sortie des signaux digitaux de données et un signal de données prêtes;

       des moyens de registre FIFO (premier entré, premier sorti) pour recevoir lesdits signaux digitaux de données à partir desdits moyens convertisseurs analogique/digital (65) et pour générer des signaux de sortie FIFO;

       des moyens de comptage d'échantillons (68) recevant ledit signal de données prêtes à partir desdits moyens convertisseurs analogique/numérique (65) et générant un signal d'interruption de données prêtes;

       des moyens processeurs de signaux digitaux (61) recevant lesdits signaux de sortie FIFO et ledit signal d'interruption de données prêtes et délivrant des signaux de base de temps et les transmissions démodulées et décodées de type à modulation à déphasage différentiel (DPSK), la correction de l'erreur de phase étant réalisée après démodulation;

       des moyens formant oscillateur (64) pour fournir des signaux de base de temps pour processeur auxdits moyens processeurs de signaux digitaux (61);

       des moyens formant mémoire (62, 63) pour fournir de l'espace mémoire pour les opérations de traitement réalisées par lesdits moyens processeurs de signaux digitaux (61); et

       des moyens contrôleurs et minuteurs (66) pour la conversion analogique/numérique recevant des signaux de base de temps et des signaux à partir desdits moyens processeurs de signaux digitaux (61) et réalisant les fonctions de contrôle et de base de temps pour les moyens convertisseurs analogique/numérique (65).
  6. Méthode pour démoduler et décoder des transmissions de type à modulation à déphasage différentiel (DPSK) comportant les opérations de:
    • filtrage des signaux reçus pour obtenir des signaux filtrés;
    • traitement desdits signaux filtrés comportant une recherche de phase et une correction de phase pour générer de l'information représentative de transmissions démodulées et décodées de type à modulation à déphasage différentiel (DPSK);

      caractérisé en ce que ladite opération de traitement comporte les opérations suivantes:
    • conversion desdits signaux filtrés en signaux digitaux; et
    • traitement digital desdits signaux digitaux pour décomposer à l'aide de moyens digitaux lesdits signaux digitaux en signaux complexes de composantes en phase et en quadrature, pour réaliser une détection de cohérence desdits signaux complexes de composantes en phase et en quadrature et fournir des signaux complexes de détection, pour réaliser ensuite une recherche de phase avant démodulation et une correction de phase de toute erreur de phase desdits signaux complexes de détection, et pour décoder de façon appropriée de l'information de type DPSK d'un Système d'Atterrissage à Micro-ondes (MLS); ladite opération de traitement digital comportant les opérations de:
    • réception desdits signaux digitaux dans des moyens processeurs de Rader (14) et transformation desdits signaux digitaux en une série de signaux complexes de composantes en phase et en quadrature à l'aide de moyens digitaux;
    • temporisation de ladite série de signaux complexes;
    • génération des conjugués de ladite série temporisée de signaux complexes;
    • réception dans des moyens de détection de cohérence (17) desdits conjugués de ladite série temporisée de signaux complexes et d'une série non temporisée directement à partir des moyens de détection de cohérence (14) et génération d'une série démodulée de valeurs complexes dont les angles de phase sont représentatifs d'une mesure de la différence de phase entre deux bits consécutifs encodés par déphasage différentiel (DPSK);
    • filtrage dans des moyens de référence de phase (21, 22, 23) de ladite série démodulée de valeurs complexes à partir desdits moyens de détection de cohérence (17) pour établir ainsi une évaluation de référence de r(t), réaliser la conjugaison complexe de ladite évaluation de référence de r(t) pour obtentir un conjugué complexe, verrouillage dudit conjugué complexe et génération d'une valeur verrouillée qui est utilisée en tant que vecteur de référence;
    • réception de ladite valeur vérouillée dans des moyens correcteurs de phase (25) et de ladite série démodulée de valeurs complexes directement à partir desdits moyens de détection de cohérence (17) et rotation de ladite série démodulée de valeurs complexes sur l'axe des réels pour obtenir un résultat réel;
    • réception dans des moyens discriminateurs (27) de durée d'impulsion dudit résultat réel desdits moyens correcteurs de phase (25), identification de la présence d'un signal d'acquisition de porteuse de 13 bits, fixation d'un signal de référence r(t) pour la durée d'une transmission par le système et génération d'un signal de détection de durée d'impulsion valide;
    • réception dans des moyens de synchronisation de données (28) dudit résultat réel obtenu à partir desdits moyens correcteurs de phase (25) et dudit signal de détection de durée d'impulsion valide à partir desdits moyens discriminateurs de durée d'impulsion (27), mise en oeuvre des algorithmes de détection d'un code de Barker caractéristique, réalisation d'une synchronisation des bits et génération d'un signal de sortie; et
    • réception dans des moyens d'échantillonnage de données (29) dudit signal de sortie à partir desdits moyens de synchronisation de données (28) et mise en oeuvre d'algorithmes d'échantillonnage dudit signal de sortie pour générer de l'information binaire de sortie représentative de transmissions démodulées et décodées de type à modulation à déphasage différentiel (DPSK).






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