Background of the Invention
This invention relates in general to frequency dividing circuits,
and more particularly, to a fractional frequency divider for providing an output
clock signal operating at a frequency equal to that of the input clock signal divided
by the ratio of two integer values.

The need to generate a lower frequency clock signal from a higher
frequency timing base signal is common in many of the electronic arts. In the
field of data communications, for example, common operating frequencies for transmitting
data over a modem link are 1200, 2400 and 9600 baud which may be realized by dividing
a 1.152 MHz input clock signal by 960, 480 and 120, respectively. The conventional
technique for generating the lower frequency output clock signal typically involves
decrementing a counter preset to an integer value N once for each period of the
input clock signal, hereinafter referred to as linear frequency division. The output
clock signal remains logic zero until the counter reaches zero at which time the
linear frequency divider generates one pulse and reloads the counter with the integer
N. Thus, the linear frequency divider produces one output period every N input
periods, i.e., the input clock is divided by N. The 1.152 MHz input clock signal
is typically developed via a dedicated crystal oscillator designed specifically
for such data communication purposes. It would be desirable to eliminate the 1.152
MHz crystal oscillator thereby simplifying the system design and reducing the manufacturing
costs. This could be accomplished by using another high frequency clock signal,
say a 10 MHz microprocessor clock already available in the system; however, in
order to develop the appropriate operating frequencies, i.e., 1200, 2400 and 9600
Hz, the 10 MHz clock signal must be divided by the non-integer values 8333.33,
4166.67 and 1041.67, respectively. In practice, the high frequency timing base
clock signal is typically divided in multiple steps of smaller increments per step
to achieve the aforementioned operational frequencies.

Consequently, fractional frequency dividers have been developed to
divide the frequency of the input clock signal by a non-integer value such as the
ratio N/D where N and D are integers and N is greater than D. One such fractional
frequency divider is the well known phase lock loop which can produce a virtually
jitter free output clock signal having a predetermined frequency and duty cycle.
However, many applications in data communications require synchronization between
the edges of the input clock signal and the lower frequency output clock signal;
a feature not available with phase locked loops. Furthermore, the phase lock loop
is relatively complex and expensive to implement requiring substantial logic circuitry
and a reference clock signal operating at a much higher frequency than even the
input clock signal being divided. Hence, the phase lock loop is not a viable solution
for many data communication applications because of the synchronization problems
and excessive complexity.

Another fractional frequency divider may be achieved with the linear
frequency divider wherein, for the example of a 7/2 (N=7, D=2) divider ratio, the
frequency divider must generate two output pulses for every seven pulses of the
input clock signal. For such an implementation, the output clock signal may remain
logic zero for five decrements of the counter followed by alternating logic one
and logic zero at the rate of the input clock signal during the next two consecutive
cycles of the input clock signal thereby producing one longer period (six cycles
of the input clock signal) and one shorter period (one cycle of the input clock
signal) over the seven cycles of the input clock signal. The repeating output clock
signal comprising alternating long and short periods is noticeably non-symmetrical
and can be even more so with other divider ratios N/D, such as N=13 and D=5. Since
the output clock signal is often applied as the input clock signal to another frequency
divider circuit further downstream for providing the multiple division steps to
reach the desired low frequency operational clock signal, the non-symmetry of the
output clock signal can be a major problem in form of undesirable jitter in the
operational clock signal.

Hence, what is needed is a frequency divider circuit for providing
an output clock signal operating at a fractional frequency of the input clock
signal while maintaining a substantially symmetrical output waveform thereby reducing
the jitter for lower frequency operational clock signals generated therefrom.

Summary of the Invention
Accordingly, an objective of the present invention is to provide an
improved fractional frequency divider.

In accordance with the above and other objectives there is provided
a frequency divider circuit responsive to first and second digital input signals
and an input clock signal for providing an output clock signal operating at a frequency
equal to that of the input clock signal divided by the ratio of the first and second
digital input signals. A controllable subtracter is responsive to the first logic
state of a digital control signal for providing a first digital output signal as
the difference between a second digital output signal applied at a first plurality
of inputs and the first digital input signal applied at a second plurality of inputs.
The controllable subtracter is responsive to the second logic state of the digital
control signal for providing the first digital output signal equal to the second
digital output signal. An adder circuit is coupled for summing the first digital
output signal of the controllable subtracter and the second digital input signal
for providing the second digital output signal at a plurality of outputs, and a
register is provided having a plurality of inputs respectively coupled to the
plurality of outputs of the adder circuit, wherein the least significant outputs
of the plurality of outputs of the register are respectively coupled to the first
plurality of inputs of the controllable subtracter, wherein the most significant
output of the plurality of outputs of the register is coupled to the controllable
subtracter for providing the digital control signal.

In another form, the frequency divider circuit is responsive to first
and second digital input signals and an input clock signal for providing an output
clock signal operating at a frequency equal to that of the input clock signal divided
by the ratio of the first and second digital input signals. A controllable adder
is responsive to the first logic state of a digital control signal for providing
a first digital output signal as the sum of a second digital output signal applied
at a first plurality of inputs and the first digital input signal applied at a
second plurality of inputs. The controllable adder is responsive to the second
logic state of the digital control signal for providing the first digital output
signal equal to the second digital output signal. A subtracter circuit is coupled
for taking the difference between the first digital output signal of the controllable
adder and the second digital input signal for providing the second digital output
signal at a plurality of outputs, and a register is provided having a plurality
of inputs respectively coupled to the plurality of outputs of the subtracter circuit,
wherein the least significant outputs of the plurality of outputs of the register
are respectively coupled to the first plurality of inputs of the controllable
adder, wherein the most significant output of the plurality of outputs of the register
is coupled to the controllable adder for providing the digital control signal.

In yet another form, the frequency divider circuit is responsive to
first and second digital input signals and an input clock signal for dividing
the frequency of the input clock signal by the ratio of the first and second digital
input signals. A first circuit is responsive to the first logic state of a digital
control signal for providing a first digital output signal as the difference between
the first digital input signal and a second digital output signal. The first circuit
is responsive to the second logic state of the digital control signal for providing
the first digital output signal equal to the second digital output signal. A second
circuit sums the first digital output signal of the first circuit and the second
digital input signal for providing the second digital output signal, and a third
circuit provides the digital control signal from a comparison the second digital
output signal of the second circuit and the first digital input signal. The digital
control signal reflects the first logic state if the second digital output signal
is greater than the first digital input signal, and the second logic state if the
second digital output signal is less than or equal to the first digital input signal.

Brief Description of the Drawings

- FIG. 1 is a simplified block diagram illustrating one embodiment of the present
invention;
- FIG. 2 is a waveform plot useful in the description of the invention; and
- FIG. 3 is a simplified block diagram illustrating an alternate embodiment of
the present invention.

Detailed Description of the Preferred Embodiment
Referring to FIG. 1, fractional frequency divider 10 is shown suitable
for manufacturing as an integrated circuit using conventional integrated circuit
processing techniques. A high frequency input clock signal, S&sub1;&sub2;, oscillating
at say 10 MHz and having a 50% duty cycle and a period of 100 nanoseconds (ns)
is applied at input 12. First and second 5-bit digital signals representing integers
D and N are applied at input bus 14 and input bus 16 which are coupled to the first
input of adder 18 and the first input of controllable subtracter 20, respectively.
The output of controllable subtracter 20 is coupled to the second input of adder
18, and the output of adder 18 is coupled to the first input of register 22, while
the second input of the latter is coupled to input bus 16. The output of register
22 is coupled to the first input of comparor 24 and to the second input of controllable
subtracter 20. Register 22 is clocked by input clock signal S&sub1;&sub2;. Input
bus 16 is coupled to the second input of comparor 24, and the output of comparor
24 is coupled to the first input of AND gate 28 and to the control input of controllable
subtracter 20. The second input of AND gate 28 is coupled to input 12, while the
output of AND gate 28 provides the lower frequency output clock signal, S&sub3;&sub0;,
at output 30.

Consider the operation of fractional frequency divider 10 wherein
the 10 MHz input clock signal S&sub1;&sub2; is to be divided by the ratio of N/D
where the integer N = 7 and the integer D = 2 thereby yielding output clock signal,
S&sub3;&sub0;, operating at a frequency of 10 MHz / 3.5, or approximately 2.857
MHz. It is understood that the values for integers N and D are selected for an
illustration of the present invention and the integers N and D may take on many
different values provided integer N is greater than integer D. The 5-bit digital
signal "00010" representing the integer D = 2 is applied at input bus 14 and the
5-bit digital signal "00111" is applied at input bus 16 for the integer N = 7.
Comparor 24 compares the 5-bit digital signal N with the 6-bit digital output signal
of register 22 and outputs a logic one if the 6-bit digital output signal of register
22 is greater than the 5-bit digital signal N; otherwise comparor 24 produces a
logic zero. If the digital output signal of comparor 24 is logic one, then the
5-bit digital signal N is subtracted from the 6-bit digital output signal of register
22 and the result is applied to the second input of adder 18; otherwise, if the
digital output signal of comparor 24 is logic zero, the 6-bit digital output signal
of register 22 is simply passed through controllable subtracter 20 to the second
input of adder 18.

To commence operation, the 5-bit digital signal N is first loaded
into 6-bit-wide register 22 as "000111" via the second input thereof at time t&sub0;
coinciding with a reset pulse (not shown). Register 22 may take on other initial
values such as "000000" which simply shifts the starting point of the repeating
output waveform. Since the control input signal of controllable subtracter 20 is
initially logic zero (digital output of register 22 is not greater than digital
signal N), the digital output signal of register 22 "000111 " is passed therethrough
and added with the 5-bit digital signal D "00010" yielding "001001" at the output
of adder 18. The 6-bit digital output signal of adder 18 is clocked into register
22 on the falling edge of input clock signal S&sub1;&sub2; at time t&sub1; as shown
in FIG. 2. The waveform plots of FIG. 2 illustrate the timing relationship between
input clock signal S&sub1;&sub2; and output clock signal S&sub3;&sub0;. Between
times t&sub1; and t&sub2;, the 6-bit digital output signal of register 22 "001001"
is compared with the 5-bit signal N "00111" via comparor 24 and the result, now
logic one, is applied at the first input of AND gate 28 and to the control input
of controllable subtracter 20 thereby subtracting the 5-bit signal N "00111" from
the 6-bit digital output signal of register 22 "001001" and adding the 5-bit signal
D "00010" yielding "001001 " - "000111 " + "00010" = "000100" at the output of
adder 18. At time t&sub2;, input clock signal S&sub1;&sub2; transitions to logic
one and combines with the logic one provided at the output of comparor 24 to produce
a logic one at output 30 during times t&sub2; through t&sub3; of FIG. 2. At time
t&sub3;, input clock signal S&sub1;&sub2; falls to logic zero causing output clock
signal S&sub3;&sub0; to follow. Also at the falling edge of the input clock signal
S&sub1;&sub2; (time t&sub3;), the 6-bit digital output signal of adder 18 "000100"
is clocked into register 22. The digital output signal of comparor 24 returns
to logic zero since the 6-bit digital output signal of register 22 is less than
the 5-bit signal N.

The cycles continue and register 22 clocks in values "000110" at
time t&sub4; and "001000" at time t&sub5;. Again the comparison of the 6-bit digital
output signal of register 22 and the 5-bit signal N between times t&sub5; and t&sub6;
finds the former greater than the latter and the digital output signal of comparor
24 becomes logic one. The logic one is combined with the logic one state of input
clock signal S&sub1;&sub2; at time t&sub6; for providing the logic one at output
30 during times t&sub6; through t&sub7; of FIG. 2. The logic one state of the digital
output signal of comparor 24 also enables controllable subtracter 20 whereby the
5-bit digital signal N "00111" is subtracted from the 6-bit digital output signal
of register 22 "001000" yielding "000001 " at the output thereof. The 5-bit digital
output signal of controllable subtracter 20 is added to the 5-bit digital signal
D and the result "000011" is clocked into register 22 at time t&sub7;. The output
clock signal S&sub3;&sub0; returns to logic zero with the transition of input clock
signal S&sub1;&sub2; to logic zero and the digital output signal of comparor 24
returns to logic zero since the 6-bit digital output signal of register 22 is again
less than the 5-bit digital signal N.

On subsequent falling edges of input clock signal S&sub1;&sub2;, register
22 clocks in values "000101 ", "000111 " and "001001 ". After the "001001 " value
is clocked into register 22 at time t&sub8;, the digital output signal of comparor
24 again enables controllable subtracter 20 since the 6-bit digital output signal
of register 22 "001001" is greater than the digital signal N "000111". The 6-bit
digital output signal of adder 18 is then "001001 " - "000111 " + "00010" = "000100".
At the rising edge of input clock signal S&sub1;&sub2; at time t&sub9;, output
clock signal S&sub3;&sub0; rises to logic one and returns to logic zero at the
falling edge of input clock signal S&sub1;&sub2;, at which time the 6-bit digital
output signal of adder 18 "0000100" is clocked into register 22 thereby completing
two periods of output clock signal S&sub3;&sub0; for seven cycles of input clock
signal S&sub1;&sub2; and returning register 22 to its value at time t&sub3;. The
periods of output clock signal S&sub3;&sub0; then repeat with symmetrical rhythm
at alternating time intervals; one lasting 300 ns (three cycles of input clock
signal S&sub1;&sub2;) and one lasting 400 ns (four cycles of input clock signal
S&sub1;&sub2;). Output clock signal S&sub3;&sub0; cycles twice for every seven
cycles of input clock signal S&sub1;&sub2;, that is, the frequency of output clock
signal S&sub3;&sub0; is 10 MHz divided by 7/2. The average of the 300 ns period
and the 400 ns period is 350 ns which translates to approximately 2.857 MHz matching
the initial calculation. The consecutive periods of output clock signal S&sub3;&sub0;
differ by no more than one period of the input clock signal.

A similar symmetry may be demonstrated for other divider ratios,
for example, with the integer N = 13 and the integer D = 5, the periods of output
clock signal S&sub3;&sub0; operate at repeating time intervals wherein one interval
(thirteen cycles of S&sub1;&sub2;) includes two consecutive 300 ns periods followed
by one 200 ns period, one 300 ns period and another 200 ns period. In combination,
the average period of output clock signal S&sub3;&sub0; ((300 + 300 + 200 + 300
+ 200) / 5) is 260 ns, or approximately 3.846 MHz. This result matches the original
calculation method of 10 MHz divided by 13/5, or 3.846 MHz. Of course, the ratio
of N/D may also be an integer value such as 26/13 wherein the periods of output
clock signal S&sub3;&sub0; are each of the same length of time.

Turning to FIG. 3, there is shown fractional frequency divider 40
as an alternate embodiment of the present invention which eliminates the need
for comparor 24. Components having similar functions are given the same reference
numbers as FIG. 1. The high frequency input clock signal S&sub1;&sub2; is applied
at input 12, and first and second 5-bit digital signals representing integers D
and N, respectively, are applied at input buses 14 and 16. The five conductors
of input bus 16 are coupled to the first inputs of NAND gates 46, 48, 50, 52 and
54, respectively, while the outputs of NAND gates 46-54 are coupled to the INB
inputs of full adders 56, 58, 60, 62 and 64. NAND gates 46-54 and full adders 56-64
collectively provide controllable subtracter 20. The Q outputs of full adders
56-64 are coupled to the INA inputs of full adders 66, 68, 70, 72 and 74, respectively,
which combine to form adder 18. The five conductors of input bus 14 are coupled
to the INB inputs of full adders 66-74, respectively. The carry-in of full adder
64 is coupled for receiving a logic one signal applied at input 75, while the carry-out
of the same is coupled to the carry-in of full adder 62. The carry-out of full
adder 62 is coupled to the carry-in of full adder 60, and the carry-out of full
adder 60 is coupled to the carry-in of full adder 58, while the carry-out of full
adder 58 is coupled to the carry-in of full adder 56. Likewise, the carry-in of
full adder 74 is coupled for receiving a logic zero signal applied at input 76,
and the carry-out of adder 74 is coupled to the carry-in of full adder 72. The
carry-out of full adder 72 is coupled to the carry-in of full adder 70, and the
carry-out of full adder 70 is coupled to the carry-in of full adder 68, while the
carry-out of full adder 68 is coupled to the carry-in of full adder 66. The Q outputs
of full adders 66-74 are coupled to the D inputs of flipflops 78, 80, 82, 84 and
86, respectively, and the Q outputs of flipflops 78-86 are coupled to the INA inputs
of full adders 56-64, respectively. The carry-out of full adder 66 is coupled to
the D input of flipflop 88, and the Q output of the latter is coupled to the second
inputs of NAND gates 46-54 and to the first input of AND gate 28. The combination
of flipflops 78-88 form register 22.

Continuing with FIG. 3, input 12 is coupled to the second input of
AND gate 28, the output of which provides the output clock signal S&sub3;&sub0;
at output 30 having a frequency equal to the frequency of the input clock S&sub1;&sub2;
divided by N/D. Input 12 is also coupled to the CLK (clock) inputs of flipflop
78-88, while input 90 is coupled to the R (reset) input of flipflop 88 and to the
S (set) inputs of flipflops 78-86. Flipflops 78-88 are edge-triggered D-type flipflops,
wherein the digital signal applied at the D input is latched to the Q output thereof
at the falling edge of input clock signal S&sub1;&sub2;. The edge-triggering feature
is used to avoid race conditions, i.e., when the output signal of flipflops 78-88
change state, the resulting output signal is propagated back to the inputs of the
same flipflops via controllable subtracter 20 and adder 18. By using edge-triggered
flipflops, it is assured that the new input signal will not propagate to the output
until the following negative-going edge of input clock signal S&sub1;&sub2;.

The operation of fractional frequency divider 40 follows the discussion
of FIG. 1 with certain distinctions as discussed below. The example using the 10
MHz input clock signal S&sub1;&sub2; divided by the ratio of N/D where the integer
N = 7 and the integer D = 2 is repeated here. Again, it is understood that the
values for integers N and D are selected for an illustration of the present invention
and the integers N and D may take on many different integer values provided integer
N is greater than integer D. A reset pulse is applied at input 90 at time t&sub0;
to load the value "011111" into register 22 which comprises flipflop 88 for the
most significant bit (MSB) and flipflops 78-86 for the five least significant
bits (LSB), respectively. Register 22 may take on other initial values such as
"100000" which simply shifts the starting point of the repeating output waveform.
The 5-bit digital signal "00010" representing the integer D = 2 is applied at input
bus 14, and the 5-bit digital signal "00111" is applied at input bus 16 for the
integer N = 7. The logic zero developed at the Q output of flipflop 88 is applied
at the first input of AND gate 28 and to the second inputs of NAND gates 46-54
thereby producing digital signal "11111 " at the outputs thereof. The combination
of the digital signal "11111 " applied at the INB inputs of full adders 56-64 with
the logic one applied at the carry-in of full adder 64 effectively adds "00000"
to the digital output signal of flipflops 78-86 "11111" applied at the INA inputs
of full adders 56-64. The 5-bit digital output signal of full adders 56-64 "11111"
is applied at the INA inputs of full adders 66-74, while the 5-bit digital signal
D "00010" is applied at the INB inputs of the same. The 6-bit digital output signal
of full adders 66-74 "11111 " + "00010" = "100001 " is clocked through to the
outputs of flipflops 78-88 on the falling edge of input clock signal S&sub1;&sub2;
at time t&sub1; as shown in FIG. 2. Notably, the MSB of the 6-bit digital output
signal of full adders 66-74 is provided at the carry-out of full adder 66 and applied
at the D input of flipflop 88. At time t&sub2;, input clock signal S&sub1;&sub2;
transitions to logic one and combines with the logic one at the Q output of flipflop
88 for providing logic one at output 30 during times t&sub2; through t&sub3; of
FIG. 2.

The logic one latched at the Q output of flipflop 88 also inverts
the 5-bit digital signal N through NAND gates 46-54 providing "11000" at the INB
inputs of full adders 56-64. Concurrently, the digital output signal of flipflops
78-86 "00001 " is applied at the INA inputs of full adders 56-64, while logic one
remains at the carry-in of fuller adder 64. The digital output signal provided
at the Q outputs of full adders 56-64 is "00001 " + "11000" + "1 " = "11010" thereby
effective taking two's complement of the 5-bit signal N and adding the 6-bit digital
output signal of register 22 which is the same as "100001" - "00111" = "11010".
The 5-bit digital output signal of full adders 56-64 "11010" is applied at the
INA inputs of full adders 66-74, while the 5-bit digital signal D "00010" is applied
at the INB inputs of the same, and the 6-bit digital output signal of full adders
66-74 "011100" is clocked through to the outputs of flipflops 78-88 on the falling
edge of input clock signal S&sub1;&sub2; at time t&sub3; as shown in FIG. 2. At
time t&sub3;, input clock signal S&sub1;&sub2; falls to logic zero causing output
clock signal S&sub3;&sub0; to follow.

The cycles continue and register 22 clocks in values "011110" at
time t&sub4; and "100000" at time t&sub5; at which time the logic one latched at
the Q output of flipflop 88 again inverts the 5-bit digital signal N through NAND
gates 46-54 providing "00000" + "11000" + "1 " = "11001 " at the Q outputs of full
adders 56-64, while the same logic one combines with the logic one state of input
clock signal S&sub1;&sub2; producing the logic one at output 30 during times t&sub6;
through t&sub7; of FIG. 2. At time t&sub7;, output clock signal S&sub3;&sub0; returns
to logic zero with the transition of input clock signal S&sub1;&sub2; to logic
zero and "011011" is clocked into register 22. On subsequent falling edges of input
clock signal S&sub1;&sub2;, register 22 clocks in values "011101 ", "011111 " and
"100001 " at time t&sub8;. At the rising edge of input clock signal S&sub1;&sub2;
at time t&sub9;, output clock signal S&sub3;&sub0; rises to logic one. The next
falling edge at time t&sub1;&sub0; returns register 22 to its value at time t&sub3;
thereby completing two periods of output clock signal S&sub3;&sub0; for seven cycles
of input clock signal S&sub1;&sub2; wherein the first period occurred between times
t&sub3; and t&sub7; and the second period occurred between times t&sub7; and t&sub1;&sub0;.
Output clock signal S&sub3;&sub0; cycles twice for every seven cycles of input
clock signal S&sub1;&sub2;, that is, the frequency of output clock signal S&sub3;&sub0;
is 10 MHz divided by 7/2, or approximately 2.857 MHz.

It is also possible to reverse the order of subtraction and addition
shown in FIG. 3 whereby element 20 becomes a controllable adder and element 18
is a full subtracter. In addition, NAND gates 46-54 are replaced with AND gates
and a logic zero is applied at input 75, while the Q output of flipflop
88 is coupled to the second inputs of AND gates 46-54. For such a configuration,
register 22 may be loaded with "100000" at time t&sub0;. Following the previous
discussion of FIG. 3 with regard to FIG. 2, the values latched into register 22
will be "011110" at time t&sub1;, "100011" at time t&sub3;, "100001" at time t&sub4;,
"011111" at time t&sub5;, "100100" at time t&sub7;, and "011110" at time t&sub8;
again returning to the value at time t&sub1; thereby completing the two repeating
periods of output clock signal S&sub3;&sub0;.

Hence, what has been described is a novel fractional frequency divider
for dividing the frequency of an input clock signal by the ratio of two integer
values while providing substantially symmetrical output periods differing by no
more than one cycle of the input clock signal which reduces the jitter for lower
frequency operational clock signals which may be generated downstream.