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Dokumentenidentifikation EP0928533 19.08.1999
EP-Veröffentlichungsnummer 0928533
Titel EINRICHTUNG FÜR EINE TEILNEHMERLEITUNGSSCHNITTSTELLENSCHALTUNG
Anmelder Telefonaktiebolaget L M Ericsson (publ), Stockholm, SE
Erfinder ERIKSSON, Hans, S-175 37 Järfälla, SE
Vertreter derzeit kein Vertreter bestellt
Vertragsstaaten DE, ES, FI, FR, GB, IT, NL, SE
Sprache des Dokument En
EP-Anmeldetag 06.11.1997
EP-Aktenzeichen 979126208
WO-Anmeldetag 06.11.1997
PCT-Aktenzeichen SE9701857
WO-Veröffentlichungsnummer 9821868
WO-Veröffentlichungsdatum 22.05.1998
EP-Offenlegungsdatum 14.07.1999
Veröffentlichungstag im Patentblatt 19.08.1999
IPC-Hauptklasse H04M 1/76

Beschreibung[en]
TECHNICAL FIELD

The invention relates generally to an arrangement for measuring the voltage across a telephone line connected to a line interface circuit.

BACKGROUND OF THE INVENTION

Line interface circuits are provided on line interface boards and are controlled by a control processor on the line interface board, the control processor being common to a plurality of line interface circuits.

In order to be able to compensate for line resistance dependent attenuation on the line, the control processor needs information about the resistance of the line connected to the respective line interface circuit A method of obtaining information about the line resistance when the current characteristic and supply voltage of the line interface circuit are known, comprises measuring the line voltage and calculating the line resistance from the measured line voltage.

To transfer the line voltage information to the control processor, either an external analog-to-digital converter or an internal analog-to-digital converter in the line interface circuit, is used today.

In the case of an external analog-to-digital converter, a separate output terminal is necessary on the line interface circuit to output an output voltage proportional to the line voltage.

With an internal analog-to-digital converter in the line interface circuit, at least one separate output terminal is needed on the line interface circuit for communication with the control processor.

For example, from patent abstracts of Japan, Vol. 14, No. 421, E-976, abstract of JP-2-161858 A, an arrangement for measuring the impedance of an external circuit, i.e. a telephone line circuit, is known which is based on measuring the circuit current. In this arrangement, a capacitor and photocouplers are connected in parallel to the external circuit. The value of the circuit current can be measured based on the time during which the both terminal voltage of the capacitor reaches a prescribed level. This known arrangement, however, still requires a separate terminal for the circuit current signal.

BRIEF DESCRIPTION OF THE INVENTION

The object of the invention is to bring about an arrangement for line voltage measurement and, thereby, line resistance calculation which does not require any extra components or any extra output terminal.

This object is achieved by an arrangement according to claim 1. The dependent claim defines a preferred embodiment of the invention.

This is attained according to the invention in that the control processor controls the detector output terminal of the line interface circuit to a first signal state at a first point of time at the same time as the line interface circuit is controlled to initiate the measurement of the line voltage. After a time interval whose lenght is proportional to the measured line voltage, the detector output terminal of the line interface circuit is controlled to a second signal state. The control processor is adapted to convert the time interval during which the detector output terminal of the line interface circuit is in the first signal state to a voltage value corresponding to the measured line voltage. Since the current characteristic and supply voltage of the line interface circuit are known, the control processor can calculate the line current on the basis of this voltage value and, thereby, also the line resistance.

Thus, the measurement can be carried out without any extra components or any extra output terminal, i.e. no extra wiring is needed on the line interface board.

BRIEF DESCRIPTION OF THE DRAWING

The invention will be described more in detail below with reference to the appended drawing, on which the single figure shows an embodiment of an arrangement according to the invention for measuring the voltage across a line connected to a line interface circuit.

PREFERRED EMBODIMENT

The single figure schematically shows a line interface circuit 1 and a control processor 2 for controlling the operating mode of the line circuit 1 via a digital interface 3.

The interface 3 has two control output terminals S1 and S2 for controlling the line-interface circuit I for measuring the voltage across the line (not shown) connected to the line interface circuit 1.

The control output terminal S 1 is connected to a switch 4 for switching the switch between a lower and an upper position. Normally, the switch 4 is in its lower position in order to transfer signals to the control processor 2 via the detector output terminal D of an inverting detector output amplifier 5 from the normal detectors of the line interface circuit 1. illustrated in the form of a block 6. These detectors which do not have anything to do with the present invention, are known per se and, therefore, are not described in this connection.

When the line voltage is to be measured in accordance with the invention, the switch 4 is switched to its upper position shown in the figure in that the control output terminal S 1 of the interface 3 is activated (brought to a high signal level) by the control processor 2 as will be described more in detail below.

In the embodiment shown, the control output terminal S2 of the interface 3 is connected to the base of a transistor Q1 whose collector is connected, on the one hand, to the base of a transistor Q6 and, on the other hand, to the anode of a diode D1 whose cathode is connected to a supply voltage VBB. The emitter of the transistor Q1 is interconnected with the emitter of a transmitter Q2 whose collector is connected to an interconnection node A.

A capacitor C1 is connected between the node A and ground. The node A is also connected to the emitter of a transistor Q3 whose base is adapted to sense the potential on that one of the two wires of the telephone line not shown, whose potential is intended to be closest to ground, usually denoted a-wire or tip wire, via a tip wire connection terminal 7.

The collector of the transistor Q3 is connected, on the one hand, to the anode of a diode D2 whose cathode is connected to the supply voltage VBB and, on the other hand, to the base of a transistor Q4 whose emitter is connected to the supply voltage VBB and whose collector is connected to the interconnection point between the base and one collector of a multi-collector transistor Q5. A second collector of the transistor Q5 is connected, on the one hand, via a resistor R1 to ground and, on the other hand, to the upper pole of the switch 4. The emitter of the transistor Q5 is connected to a supply voltage VCC.

Moreover, a current generator I1 is connected between the supply voltage VCC and the interconnection point between the emitters of the transistors Q1 and Q2.

The node A is, furthermore, connected to the cathode of a diode D3 whose anode is adapted to sense the voltage on the second wire, usually denoted b-wire or ring wire, of the line (not shown) connected to the line interface circuit 1 via a ring wire connection terminal 8. The b-wire (not shown), is the wire whose potential is intended to be closest to the supply voltage VBB.

Finally, the node A is connected to the collector of the transistor Q6 whose emitter is connected to the supply voltage VBB and whose base, as above, is connected to the interconnection point between the collector of the transistor Q1 and the anode of the diode D1.

The base of the transistor Q2 is connected to a DC source 9.

Normally, the base of the transistor Q 1 is at a signal level which is lower than the signal level at the base of the transistor Q2, i.e. the transistor Q1 is normally conducting, while the transistor Q2 is cut off. Thus, the current from the current generator 11 normally flows through the transistor Q1 and the diode D1. This current is mirrored to the collector of the transistor Q6 and will be drawn through the diode D3 in such a manner that the voltage in the node A will be a diode voltage drop of the diode D3 below the voltage of the ring wire (not shown), i.e. the voltage of the ring wire connection terminal 8.

Thus, the capacitor C1 will normally be charged to this voltage.

To measure the line voltage across the line (not shown) connected to the connection terminals 7 and 8, the control processor 2 is adapted to apply to the base of the transistor Q1 via the control output terminal S2 of the interface 3, a signal level which is high in comparison with the signal level that the DC source 9 applies to the base of the transistor Q2.

This point of time is registered by the control processor 2 as a starting point of time for the measurement.

At the same time, the control output terminal S1 of the interface 3 is activated, bringing the switch 4 to its position illustrated in the figure. Hereby, the input terminal of the amplifier 5 is grounded via the resistor R1. Therefore, the signal level on the output terminal of the amplifier 5 will be low. Since the amplifier 5 is inverting, the signal level will be high on the output terminal D which ensures that the signal level on the terminal D will be high irrespective of its previous signal level.

When the signal level on the base of the transistor Q1 is higher than the signal level on the base of the transistor Q2, the transistor Q1 is cut off while the transistor Q2 becomes conducting. The current from the current generator I1 will instead flow through the transistor Q2 and start to recharge the capacitor C1.

When the voltage across the capacitor C1, i.e. the voltage in the node A, reaches such a value relative to the voltage on the base of the transistor Q3, i.e. the voltage on the tip wire connection terminal 7, that the transistor Q3 starts to conduct, the current from the current generator I1 will flow through the transistor Q3 and the diode D2. This current is mirrored to the collector of the transistor Q4. The collector current of the transistor Q4 is drawn from the collector interconnected with the base of the transistor Q5 and is mirrored to the second collector of the multi-collector transistor Q5. Thus, the current flows through the resistor R1 and causes a voltage across this resistor. The voltage across the resistor R1 is coupled via the switch 4 in its illustrated position to the input terminal of the amplifier 5 which causes the signal level to become low on the output of the amplifier 5. That the signal level on the output terminal D goes low is registered by the control processor 2 as the ending point of time for the measurement.

Thus, the detector output terminal D of the line interface circuit 1 goes low after a time interval corresponding to the time it took to recharge the capacitor C1. During this time interval, the capacitor C1 has been recharged to a voltage which is proportional to the voltage across the line (not shown) connected to the tip and ring wire connection terminals 7 and 8, respectively.

The control processor 2 is adapted to measure this time interval whose length is proportional to the line voltage. Based on the calculated voltage value, the control processor 2 is adapted to calculate the line current since the current characteristic and supply voltage of the line interface circuit are known. From the line current value, the control processor is adapted to calculate the line resistance.


Anspruch[de]
  1. Anordnung zum Messen einer Leitungsspannung, umfassend eine Leitungsschnittstellenschaltung (1) mit welcher ein Steuerprozessor (2) verbunden ist, wobei der Steuerprozessor (2) dazu ausgestaltet ist, einerseits die Betriebsart der Leitungsschnittstellenschaltung (1) zu steuern und andererseits den Zustand einer mit der Leitungsschnittstellenschaltung (1) verbundenen Leitung über einen Detektorausgangsanschluss D der Leitungsschnittstellenschaltung (1) zu überwachen, dadurch gekennzeichnet,
    • dass der Steuerprozessor (2) dazu ausgestaltet ist, die Leitungsschnittstellenschaltung (1) zu steuern, so dass sie einerseits zu einem ersten Zeitpunkt gewährleistet, dass ihr Detektorausgangsanschluss (D) in einem ersten Signalzustand ist, und andererseits zu diesem ersten Zeitpunkt eine Messung der Leitungsspannung einzuleiten,
    • dass die Leitungsschnittstellenschaltung (1) dazu ausgestaltet ist, zu einem zweiten Zeitpunkt, nach einem Zeitintervall, dessen Länge proportional zu der gemessenen Leitungsspannung ist, den Detektorausgangsanschluss (D) in einen zweiten Signalzustand zu bringen, und
    • dass der Steuerprozessor (2) dazu ausgestaltet ist, das Zeitintervall, in welchem der Detektorausgangsanschluss (D) der Leitungsschnittstellenschaltung (1) in dem ersten Signalzustand ist, in einen Spannungswert, welcher der Leitungsspannung entspricht, umzuwandeln.
  2. Anordnung gemäß Anspruch 1, dadurch gekennzeichnet, dass der Steuerprozessor (2) dazu ausgestaltet ist, aus dem Spannungswert, welcher der Leitungsspannung entspricht, den Leitungswiderstand zu berechnen.
Anspruch[en]
  1. Arrangement for measuring a line voltage comprising a line interface circuit (1) to which a control processor (2) is connected, the control processor (2) being adapted, on the one hand, to control the operating mode of the line interface circuit (1) and, on the other hand, monitor the status of a line connected to the line interface circuit (1), via a detector output terminal (D) of the line interface circuit (1), characterized in
    • that the control processor (2) is adapted to control the line interface circuit (1) to, on the one hand, ensure at a first point of time that its detector output terminal (D) is in a first signal state and, on the other hand, at that first point of time initiate measurement of the line voltage,
    • that the line interface circuit (1) is adapted, at a second point of time, to bring the detector output terminal (D) to a second signal state after a time interval whose length is proportional to the measured line voltage, and
    • that the control processor (2) is adapted to convert the time interval during which the detector output terminal (D) of the line interface circuit (1) is in the first signal state, to a voltage value corresponding to the line voltage.
  2. The arrangement according to claim 1, characterized in that the control processor (2) is adapted to calculate the line resistance from the voltage value corresponding to the line voltage.
Anspruch[fr]
  1. Configuration pour mesurer une tension de ligne comprenant un circuit d'interface de ligne (1) auquel un processeur de commande (2) est connecté, le processeur de commande (2) étant adapté, d'une part, pour commander le mode de fonctionnement du circuit d'interface de ligne (1) et, d'autre part, contrôler l'état d'une ligne connectée au circuit d'interface de ligne (1), par l'intermédiaire d'un terminal de sortie d'un détecteur (D) du circuit d'interface de ligne (1),

    caractérisée en ce
    • que le processeur de commande (2) est adapté pour commander le circuit d'interface de ligne (1) afin, d'une part, d'assurer à un premier point de temps que son terminal de sortie d'un détecteur (D) est dans un premier état de signal et, d'autre part, à ce premier point de temps, de commencer la mesure de la tension de ligne,
    • que le circuit d'interface de ligne (1) est adapté, à un deuxième point de temps, pour amener le terminal de sortie d'un détecteur (D) à un deuxième état de signal après un intervalle de temps dont la durée est proportionnelle à la tension de ligne mesurée, et
    • que le processeur de commande (2) est adapté pour convertir l'intervalle de temps durant lequel le terminal de sortie d'un détecteur (D) du circuit d'interface de ligne (1) est dans le premier état de signal, à une valeur de tension correspondant à la tension de ligne.
  2. Configuration selon la revendication 1,caractérisée en ce que le processeur de commande (2) est adapté pour calculer la résistance de ligne à partir de la valeur de tension correspondant à la tension de ligne.






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G Physik
H Elektrotechnik

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