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Dokumentenidentifikation EP0661803 02.09.1999
EP-Veröffentlichungsnummer 0661803
Titel Phasendifferentielle Schaltung mit hoher Synchronisierung
Anmelder NEC Corp., Tokio/Tokyo, JP
Erfinder Yoshida, Makoto, c/o NEC Corporation, Tokyo, JP
Vertreter derzeit kein Vertreter bestellt
DE-Aktenzeichen 69419711
Vertragsstaaten DE, FR, GB
Sprache des Dokument En
EP-Anmeldetag 28.12.1994
EP-Aktenzeichen 941208704
EP-Offenlegungsdatum 05.07.1995
EP date of grant 28.07.1999
Veröffentlichungstag im Patentblatt 02.09.1999
IPC-Hauptklasse H03F 3/30
IPC-Nebenklasse H03K 5/15   

Beschreibung[en]
Background of the Invention Field of the Invention

The present invention relates to a phase differential circuit demanding high synchronicity and precision.

Description of the Prior Art

In digital circuitries, differential phase signals having a low skew, i.e. high synchronicity, between an original signal and its inverted signals are required. An example of a conventional method of generating such signals is shown in FIG. 2. An original signal is inputted into an input terminal 201, inverted signals of the original signal are produced in inverting circuits 210-215, and the inverted signals are outputted from an output terminal 203. In the meanwhile, non-inverted signals of the original signal are obtained from an output terminal 202 via delay circuit 204-209 having adjustable delay times produced with a variable capacitor 216. In the conventional technique, phase differentials are minimized using this circuit by adjusting the delay times so as to obtain the least possible phase difference between the inverted signals from the output terminal 203 and the non-inverted signal outputted from the output terminal 202. The delay time adjustments are generally made by adjusting the variable capacitor 216, but it is also possible to adjust the driving power of the transistors 204, 205.

To produce digital signal waveforms having minimal phase differences, for example 200 ps, in the conventional phase differential technique described above, there was a problem that the requirements for adjustable capacitors and driving circuits necessarily led to a large area for integrated circuit fabrication, which is contrary to the requirements of advanced compact devices.

From JP-A-59-97222 there is known a clock pulse generating circuit. To attain a two-phase clock pulse having less time delay the input of a first row having two stages of inverters connected in series and the input of the second row having a gate and an inverter connected in series are made common, and the output signal of the inverter of the first stage of the first row is given to both gate electrodes of the gate. In an other embodiment the second row consists of three stages of inverters the input terminal of which is in common with the first row.

Patent abstracts of Japan, vol. 15, No. 209, and JP-A-03-058608 are directed to increase the amplitude of a phase inverting voltage and the amplitude of a reference voltage more than the amplitude of an input signal by applying phase inversion amplification to an input signal with a common source FET so as to obtain a phase inverted voltage and using a common gate FET so as to amplify the input signal thereby obtaining the reference voltage.

Summary of the Invention

It is therefore the object of the present invention to provide an inverting circuit applicable to making of advanced compact devices for generating non-inverted and inverted output signals, both signals having a synchronicity to an original input signal and which do not require adjustable capacitors or driving circuit for their generation.

This objective is achieved in an inverting circuit means for generating an inverted digital signal and a non-inverted signal as defined in independent claim 1. Dependent claims 2 and 3 define particular embodiments of the invention.

An inverting circuit comprises : a first N-MOS transistor for pull-down of the non-inverted signal output of the original input signal, a second P-MOS transistor for pull-up of the inverted output signal of the original input signal, a third P-MOS transistor for driving the second P-MOS transistor, and a fourth N-MOS transistor for potential control of the first N-MOS transistor. The first N-MOS transistor has a source terminal at a ground potential and a drain terminal connected to an output terminal of the non-inverted signal. The second P-MOS transistor has a gate terminal a a ground potential and a drain terminal connected to an output terminal of the inverted signal. And a gate terminal of the first N-MOS transistor, a source terminal of the second P-MOS transistor, a drain terminal of the third P-MOS transistor and a drain terminal of the fourth N-MOS transistor are all connected to a common point. According to an aspect of the circuit means of the above construction, during the transition from the ground potential to an operating potential, the gate-to-source voltage of the pull-down transistor circuit becomes exactly the same as that of the pull-up transistor circuit.

Another aspect according to an embodiment of the invention is that static voltage-current characteristics of gate-to-source voltage vs. drain-to-source current for the N-MOS transistors and the P-MOS transistors are related by a specific ratio so as to produce a high synchronicity between an original input signal and its non-inverted and inverted signals. The gate-to-source voltage vs. the drain-to-source current characteristics in a pair of pull-up P-MOS transistors are matched with those in a pair of pull-down N-MOS transistors by adjusting the channel lengths, widths and the direction of the current. Matching of the operating characteristics of the pull-up and pull-down transistors generates time-dependent traces of the output signals to be the same, and promotes the production of differential phase signals having high synchronicity and precision.

Brief Description of the Drawings

FIG. 1 is a circuit configuration of the present embodiment.

FIG. 2 is a circuit configuration of the conventional differential buffer.

FIG. 3 is a timing chart for the output signal waveforms associated with the present embodiment.

Detailed Description of the Invention

FIG. 1 shows a circuit configuration of the embodiment comprising a pull-down transistor 4 and a pull-up transistor 8 corresponding to a pull-down N channel MOS transistor 4 (N-MOS 4) for providing a non-inverted output signal 14 and a pull-up P channel MOS transistor 8 (P-MOS 8) for providing an inverted output signal 13. Transistor 4 and transistor 8 respectively for pull-up and pull-down portions of the inverting circuit are fabricated so that their static characteristic curves of the gate-to-source voltage vs. the drain-to source currents are highly matched by adjusting the channel lengths, channel widths and current directions within the channels, for example. Therefore, the current driving capacity for transistor 4 and 8 are matched. Similarly, transistor 2 and transistor 5, respectively, for pull-down and pull-up portions, must be fabricated so that their static characteristics curves and the current driving capacity are matched.

The source terminal of N-MOS 4 and the gate terminal of P-MOS 8 are at the ground potential GND, and the gate terminal of N-MOS 4 and the source terminal of P-MOS 8 are at the same potential, and are connected to the drain terminal (node B) of a driving transistor P-MOS 7.

The source terminal of P-MOS 5 and the gate terminal of N-MOS 2 are at the power supply potential VDD (terminal 12), and the gate terminal of P-MOS 5 and the source terminal of N-MOS 1 are at the same potential, and are connected to the drain terminal (node A) of a driving transistor N-MOS 1.

N-MOS 1 and P-MOS 6 compose the CMOS invertor. The output terminal of this CMOS invertor is connected to the node A. N-MOS 3 and P-MOS 7 also compose the CMOS invertor. The output terminal of this CMOS invertor is connected to the node B.

Let us suppose that the potential of the input terminal 15 is VDD. The non-inverted output signal 14 is at potential VDD, and the inverted output signal is at potential GND.

FIG. 3 is a timing chart showing the output waveform timings for output signals generated in the embodiment circuit. The potential at point B is kept at ground potential GND by a potential control transistor N-MOS 3.

When the potential of the input terminal 15 is altered from VDD to GND, the potential at point B changes from GND to VDD. At this time, the gate-to-source voltage of the pull-down transistor 4 for outputting non-inverted signal is exactly the same as that of the pull-up transistor 8 for outputting inverted signal. In other words, the potential at point B is the same as the absolute value of the gate-to-source voltage of the transistors 8 and 4.

The behavior of the circuit in the case of altering the voltage of the input terminal 15 from GND to VDD is also identical. In this case, the non-inverted output terminal 14 is at the GND potential, and the inverted output terminal 13 is at the VDD potential.

The potential of the point A is maintained at VDD by a potential control transistor P-MOS 6. When the potential of the input terminal 15 is altered from GND to VDD, the potential at the point A is altered from VDD to GND as shown in FIG. 3. At this time, the gate-to-source voltage of the pull-up transistor 5 for outputting non-inverted signal is exactly the same as that of the pull-down transistor 2 for outputting the inverted output signal. In other words, the potential at point A is the same as the absolute value of the gate to source potentials of the transistors 2 and 5.

It should be noted that the current driving capacity for a P-driving transistor P-MOS 7 (third transistor) which is connected in series with the pull-up transistor P-MOS 8 must be sufficiently high, for example, not less than twice that for the pull-up transistor P-MOS 8. Similarly, it is necessary that the current driving capacity for a N-driving transistor N-MOS 1 be sufficiently high in comparison with that for the pull-down transistor N-MOS 2. This is required so that the voltage transition at A and B points will be performed quickly, so as to minimize the difference in switching times caused by the difference in the threshold values in the gate-to-source voltage of the pull-up P-MOS 8 and the pull-down N-MOS 4 on the one hand, and the pull-up P-MOS 5 and the pull-down N-MOS 2 on the other.

It is also necessary to match the voltage trace of the drain-to-source voltage of pull-up P-MOS 8 with that of pull-down N-MOS 4; and to match the voltage trace of the drain-to-source voltage of the pull-down N-MOS 2 with that of the pull-up P-MOS 5. For this reason, during the output voltage transition stage, the drain-to-source voltages of the P-driving transistor P-MOS 7 and the N-driving transistor N-MOS 1 should be sufficiently small in comparison with those of the pull-up P-MOS 8 and the pull-down N-MOS 2.

To provide the non-inverted signal output terminal 14 and the inverted signal output terminal 13 with the same capacitive loading conditions, it is advisable to connect a buffer device having the same input capacity to each terminal, in order to realize a more preferable phase difference.

As described above, the phase differential generation circuit of this invention generates a non-inverted signal and an inverted signal having a high synchronicity to the original signal without the necessity of having an output signal timing adjusting device. It follows that variable capacitors or conventional driving circuitry are not necessary, thus permitting to realize precision phase differential buffer circuit within a small layout area.

It is clear that other types circuitry can be devised or the embodiment circuit can be simplified without departing from the basic principle outlined above that time-dependency in inverted and non-inverted signals to an original input signal can be produced by carefully matching the gate-to-source voltage vs. drain-to-source characteristics of the pull-up and pull down transistors, and controlling their output potentials.


Anspruch[de]
  1. Phasenverschiebungsschaltung, die folgendes aufweist: eine erste Inverterschaltung (1, 6) zum Invertieren eines Eingangssignals, eine zweite Inverterschaltung (3, 7) zum Invertieren des Eingangssignals, einen ersten Ausgangstransistor (5), der zwischen einem ersten Leistungsversorgungsanschluß (12) und einem ersten Ausgangsanschluß (14) angeschlossen ist, mit einem Gateanschluß, der mit einem Ausgangsanschluß des ersten Inverters verbunden ist, einen zweiten Ausgangstransistor (4), der zwischen einem zweiten Leistungsversorgungsanschluß und dem ersten Ausgangsanschluß angeschlossen ist, mit einem Gateanschluß, der mit einem Ausgangsanschluß des zweiten Inverters verbunden ist, eine erste Übertragungseinrichtung (2), die zwischen dem Ausgangsanschluß des ersten Inverters und einem zweiten Ausgangsanschluß (13) angeschlossen ist, zum Durchführen eines EIN- oder AUS-Schaltens in Antwort auf einen Pegel des Ausgangsanschlusses des ersten Inverters, eine zweite Übertragungseinrichtung (8), die zwischen dem Ausgangsanschluß des zweiten Inverters und dem zweiten Anschluß (13) angeschlossen ist, zum Durchführen eines EIN- oder AUS-Schaltens in Antwort auf einen Pegel des Ausgangsanschlusses des zweiten Inverters, wobei die Stromtreiberkapazität des ersten Ausgangstransistors (6) und die Stromtreiberkapazität der ersten Übertragungseinrichtung (2) angepaßt sind, und wobei die Stromtreiberkapazität des zweiten Ausgangstransistors (4) und die Stromtreiberkapazität der zweiten Übertragungseinrichtung (8) angepaßt sind.
  2. Phasenverschiebungsschaltung nach Anspruch 1, wobei der erste Ausgangstransistor (5) ein P-Kanal-MOS-Transistor ist, und der zweite Ausgangstransistor (4) ein N-Kanal-MOS-Transistor ist.
  3. Phasenverschiebungsschaltung nach Anspruch 2, wobei die erste Übertragungseinrichtung (2) ein N-Kanal-MOS-Transistor mit einem Gateanschluß ist, der mit dem ersten Leistungsversorgungsanschluß verbunden ist, und die zweite Übertragungseinrichtung (8) ein P-Kanal-Transistor mit einem Gateanschluß ist, der mit dem zweiten Leistungsversorgungsanschluß verbunden ist.
Anspruch[en]
  1. A phase differential circuit comprising, a first invertor circuit (1,6) for inverting an input signal, a second invertor circuit (3,7) for inverting said input signal, a first output transistor (5) connected between a first power supply terminal (12) and a first output terminal (14) having a gate terminal connected to an output terminal of said first invertor, a second output transistor (4) connected between a second power supply terminal and said first output terminal having a gate terminal connected to an output terminal of said second invertor, a first transfer means (2) connected between said output terminal of said first invertor and a second output terminal (13) for performing ON or OFF response to a level of said output terminal of said first invertor, a second transfer means (8) connected between said output terminal of said second invertor and said second terminal (13) for performing ON or OFF response to a level of said output terminal of said second invertor, wherein the current driving capacity of said first output transistor (5) and the current driving capacity of said first transfer means (2) are matched, the current driving capacity of second output transistor (4) and the current driving capacity of second transfer means (8) are matched.
  2. A phase differential circuit as claimed in claim 1, wherein said first output transistor (5) is a P channel MOS transistor, said second output transistor (4) is a N channel MOS transistor.
  3. A phase differential circuit as claimed in claim 2, wherein said first transfer means (2) is a N channel MOS transistor having a gate terminal connected to said first power supply terminal, said second transfer means (8) is a P channel transistor having a gate terminal connected to said second power supply terminal.
Anspruch[fr]
  1. Circuit de différence de phase comprenant un premier circuit inverseur (1, 6) pour inverser un signal d'entrée, un second circuit inverseur (3, 7) pour inverser ledit signal d'entrée, un premier transistor de sortie (5) connecté entre une première borne d'alimentation électrique (12) et une première borne de sortie (14) ayant une borne de grille connectée à une borne de sortie dudit premier inverseur, un second transistor de sortie (4) connecté entre une seconde borne d'alimentation électrique et ladite première borne de sortie ayant une borne de grille connectée à une borne de sortie dudit second inverseur, un premier moyen de transfert (2) connecté entre ladite borne de sortie dudit premier inverseur et une seconde borne de sortie (13) pour produire une réponse en tout ou rien à un niveau de ladite borne de sortie dudit premier inverseur, un second moyen de transfert (8) connecté entre ladite borne de sortie dudit second inverseur et ladite seconde borne (13) pour produire une réponse en tout ou rien à un niveau de ladite borne de sortie dudit second inverseur, la capacité d'attaque en courant dudit premier transistor de sortie (5) et la capacité d'attaque en courant dudit premier moyen de transfert (2) étant adaptées, la capacité d'attaque en courant du second transistor de sortie (4) et la capacité d'attaque en courant du second moyen de transfert (8) étant adaptées.
  2. Circuit de différence de phase selon la revendication 1, dans lequel ledit premier transistor de sortie (5) est un transistor MOS à canal P, ledit second transistor de sortie (4) est un transistor MOS à canal N.
  3. Circuit de différence de phase selon la revendication 2, dans lequel ledit premier moyen de transfert (2) est un transistor MOS à canal N ayant une première borne de grille connectée à ladite première borne d'alimentation électrique, ledit second moyen de transfert (8) est un transistor à canal P ayant une borne de grille connectée à ladite seconde borne d'alimentation électrique.






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