PatentDe  


Dokumentenidentifikation EP0830729 21.11.2002
EP-Veröffentlichungsnummer 0830729
Titel KLEINSTLEISTUNGSVERSTÄRKER FÜR DEN GESAMTEN SPEISESPANNUNGSBEREICH
Anmelder Analog Devices Inc., Norwood, Mass., US
Erfinder BUTLER, R., James, San Jose, US
Vertreter Grünecker, Kinkeldey, Stockmair & Schwanhäusser, 80538 München
DE-Aktenzeichen 69528606
Vertragsstaaten DE, FR, GB
Sprache des Dokument EN
EP-Anmeldetag 31.08.1995
EP-Aktenzeichen 959316605
WO-Anmeldetag 31.08.1995
PCT-Aktenzeichen PCT/US95/11077
WO-Veröffentlichungsnummer 0096039743
WO-Veröffentlichungsdatum 12.12.1996
EP-Offenlegungsdatum 25.03.1998
EP date of grant 16.10.2002
Veröffentlichungstag im Patentblatt 21.11.2002
IPC-Hauptklasse H03F 3/30

Beschreibung[en]
BACKGROUND OF THE INVENTION Field of the Invention

The present invention generally relates to bipolar micro-power rail-to-rail amplifiers, and more specifically to a micro-power output stage that is capable of delivering a high ratio of load current to no load idle current.

Description of the Related Art

Battery powered amplifiers may spend long periods of time in an "idle" condition with no input signal, or with intermittent input signals as in the case of voice signals. Power dissipated in these idle periods is wasted and may shorten the lifetime of the battery.

The output stage of a rail-to-rail amplifier is designed to deliver a specified amount of signal power to a load and to consume low power during the idle periods. A standard measure for an amplifier's power consumption is its no load idle current. Present bipolar output stages contribute at least 100µA of no load idle current and require a relatively large number of components to deliver the desired signal gain, suitably an open loop gain of one million and a closed loop gain of one. The amount of power dissipated during idle periods is too high for applications such as battery powered instrumentation and telecommunication equipment. Furthermore, the number of components and heat dissipation requirements increase the physical dimensions of the integrated circuit, which increases its cost.

Analog Devices, Inc. produces a "Precision Rail-to-Rail Input & Output Operational Amplifier" OP284 that has the ability to swing rail-to-rail at both the input and output. The OP284 has a low supply current of approximately 800µ per amplifier at room temperature. The OP284's output stage uses a constant current source to supply the gain current needed to achieve sufficient signal gain, and hence idles at a relatively high current level.

Analog Devices, Inc. also produces a "Micropower Sin-gle-Supply Rail-to-Rail Input/Output Op Amp" OP291. The OP291 has a low supply current of 300µ per amplifier and consumes a quiescent current of 600µ. The OP291's output stage uses output transistor that have 180x relative emitter sizes to achieve the desired gain. This requires a lot of space on the chip. Furthermore, the output stage requires a high number of components.

SUMMARY OF THE INVENTION

The present invention seeks to provide a bipolar micro-power rail-to-rail operational amplifier having a low complexity output stage that provides a high ratio of output load current to no load idle current.

This is accomplished with a dual differential input stage that converts a rail-to-rail input voltage into dual differential currents, a transimpedance stage that converts the differential currents into a single ended drive voltage at a gain node, and an output stage that amplifies changes in the drive voltage to produce a rail-to-rail output voltage at an output terminal.

The output stage includes first and second output transistors of opposite conductivities whose current circuits are connected in series at the output terminal between high and low voltage supplies. A gain transistor has a base that is held at a constant reference voltage, an emitter that is connected to the base of the npn, and a collector that conducts a gain current. A regenerative current source supplies current to the gain transistor by returning the gain current in a regenerative feedback loop to its emitter so that the current source idles at a low current but is capable of supplying much higher currents. A voltage element responds to the gain current by applying a control voltage that varies approximately logarithmically at low gain currents and approximately linearly at high gain currents, to the base of the second output transistor so that its output current varies approximately proportional to the gain current at low levels and as an approximately exponential function of said gain current at high levels.

A control transistor having a base, a collector and an emitter that is connected to the base of said first output transistor and the emitter of said gain transistor. The control transistor responds to the drive voltage at its base by modulating the base-emitter voltages of the first output and gain transistors in opposite directions so that their output currents are unbalanced thereby generating a load current at the output terminal which adjusts the output voltage. The control transistor also conducts a control current that stabilizes the feedback loop.

For a better understanding of the invention, and to show how the same may be carried into effect, reference will now be made, by way of example, to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

  • FIG. 1 is a block diagram of a micro-power rail-to-rail operational amplifier in accordance with the present invention;
  • FIG. 2 is a simplified schematic diagram of an output stage for the operational amplifier shown in FIG. 1; and
  • FIGs. 3a, 3b and 3c are together a schematic diagram of a preferred embodiment of the operational amplifier shown in FIG. 1.

DETAILED DESCRIPTION OF THE INVENTION

As shown in FIG. 1, a micro-power rail-to-rail operational amplifier (opamp) 10 includes a transconductance input stage 12 that converts a rail-to-rail differential input voltage signal Vin into dual differential currents Ilow+, Ilow- and Ihigh+, Ihigh-, a transimpedance stage 14 that converts the differential currents into a single ended drive voltage Vd at a gain node 16, and an output stage 18 that amplifies changes in Vd to produce a rail-to-rail output voltage Vo at an output terminal 20. As shown, amplifier 10 is a single-sided supply amplifier having a high supply voltage Vcc of 5V and a low supply voltage Vee of ground potential. An external load 22 is preferably connected between output terminal 20 and Vee. The input and transimpedance stages suitably provide 60 dB of gain, and output stage 18 suitably provides another 60 dB of gain. Hence, amplifier 10, operating open loop, would produce a 1V output voltage Vo in response to a 1µ differential input voltage Vin.

In practice, Vin is applied to the input stage's non-inverting terminal 24 and output terminal 20 is connected to the input stage's inverting terminal 26 to provide negative feedback that forces output voltage Vo to substantially follow Vin. An error voltage Ve = (Vin-Vo) of between approximately 0 and 5µV is maintained across the input terminals so that the output voltage Vo follows Vin. In this closed loop configuration, amplifier 10 is a broadband unity gain amplifier with low signal distortion that delivers a controlled amount of signal power to external load 22.

Amplifier 10 is said to be in balance when it delivers zero load current. Under no load conditions, amplifier 10 can not source any load current, and hence is always balanced. Under load conditions, amplifier 10 is only balanced when Vo=Vee. During idle periods, Vo will fall to near Vee but will not be perfectly balanced due to practical limitations in the output stage. In the preferred embodiment of the invention, amplifier 10 supplies a maximum of approximately 5mA of load current IL to load 22 while drawing a no load idle current of only approximately 50µA so that the amplifier consumes a low amount of power during idle periods.

Input stage 12 preferably includes a pair of differential input circuits 28 and 30, which have identical circuit topologies except that their transistor conductivities are reversed. Input circuit 28 operates for input voltages Vin down to Vee, but shuts down when Vin gets to within two diode voltages of a high supply voltage Vcc. Similarly, input circuit 30 operates for input voltages Vin up to Vcc but shuts down when Vin gets to within two diode voltages of Vee. Together input circuits 28 and 30 allow Vin to swing between approximately the low and high supply voltages Vee and Vcc, respectively, without clipping. Both input circuits are turned on over a majority of the input signal range and one of the two are turned on when Vin approaches one of the supply voltages. Alternately, the input circuits could be controlled so that only one was turned on at a time.

Input circuits 28 and 30 produce differential currents Ilow+, Ilow- and Ihigh+, Ihigh-. Under no load conditions, amplifier 10 does not supply load current at output terminal 20 and is said to be in balance so that these currents are equal. Under loaded conditions, the differential currents are imbalanced to supply load current IL at terminal 20 and maintain Vo at substantially Vin. When driving load 22, input circuits 28 and 30 respond to changes in Vin, and hence Ve by adjusting differential currents Ilow+ and Ihigh+ so that they move in opposite directions and adjusting Ilow- and Ihigh- so that they move in opposite directions to modulate the load current supplied at terminal 20. The negative feedback maintains the differential currents at approximately their no load values.

Transimpedance stage 14 responds to changes in the differential currents produced by input stage 12 by reducing drive voltage Vd over a range of approximately 0 to 5mV relative to a known reference voltage to produce a drive current at gain node 16. Input circuit 28 and a high side of transimpedance stage 14 are tied through resistors R1 and R2 to Vcc to supply differential currents Ilow+, Ilow- to input circuit 28 and currents I1, I2 to the transimpedance stage. Similarly, input circuit 30 and a low side of transimpedance stage 14 are tied through resistors R3 and R4 to Vee to draw differential currents Ihigh+, Ihigh- from input circuit 30 and currents I3, I4 from the transimpedance stage. Under no load conditions, currents I1 through I4 are substantially the same and drive voltage Vd remains at the reference voltage so that the drive current at gain node 16 remains constant. Under loaded conditions, the differential currents are imbalanced which reduces drive voltage Vd and the amount of drive current supplied at gain node 16.

Transimpedance stage 14 is designed so that the voltages across resistors R1 and R2 are substantially constant. Therefore, changes in Ilow+ and Ilow- induce equal and opposite changes in I1 and I2. Transimpedance stage 14 forces I3 to be substantially equal to I1 so that changes in Ilow+ and Ihigh+ adjust the voltage across resistor R3 to reflect the change in Vin.

Transimpedance stage 14 is further designed so that the voltage across resistor R4 tries to follow the voltage across R3. This causes currents I2 and I4 to move in opposite directions in response to a change in Vin thereby modulating drive voltage Vd relative to the reference voltage and adjusting the drive current at gain node 16.

Drive voltage Vd is preferably applied to a buffer circuit 32, which shifts Vd towards the low supply Vee by an amount substantially equal to the nominal voltage across resistor R3. This is done to set the value of Vd at balance to the particular reference voltage level and to reduce the amplifier's offset voltage. Circuit 32 also buffers the transimpedance stage so that it does not have to directly supply the drive current to output stage 18.

Output stage 18 responds to the level shifted and buffered voltage signal, also referred to as Vd, by supplying load current IL at output terminal 20 to produce output voltage signal Vo across external load 22. Output stage 18 uses a regenerative current source to provide an internal gain current that is used to control signal gain. The regenerative current source supplies the gain current in a regenerative feedback loop so that the gain current can vary over a wide range, approximately 0µA to approximately 110µA, in response to changes in drive voltage Vd. This allows output stage 18 to supply the large amount of gain current needed to provide a high gain output stage while idling under no load conditions at approximately 3µA. Under loaded conditions, the regenerative current source will idle at a somewhat higher level because in practice output stage 18 can not be driven all the way to ground, and hence a small current will flow through the load.

By supplying gain current as it is demanded by changes in Vin, output stage 18 lowers the average power consumed by the amplifier without sacrificing performance. In the preferred embodiment amplifier 10 consumes a total no load idle current of approximately 50µA with only approximately 8µA being consumed by the output stage. The maximum load current is 5mA so that the ratio of load current to no load idle current is approximately one thousand. Furthermore, the regenerative current source is self-limiting, which prevents the gain current from increasing unchecked in response to an extreme variation in Vd and destroying the amplifier. The regenerative current source requires relatively few components and a moderate amount of chip space.

FIG. 2 is a schematic diagram of output stage 18 shown in FIG. 1. Output stage 18 comprises a 10x pnp output transistor Q1 whose emitter 34 is connected to Vcc and a 4x npn output transistor Q2 whose emitter 36 is connected to Vee. Their collectors 38 and 40 are connected together at output terminal 20. The 10x and 4x designations represent the transistors emitter sizes relative to standard 1x size, and are chosen to provide proper bias conditions for the amplifier. In general, current flows from the supply Vcc through transistors Q1 and Q2 and into negative supply Vee. Under no load conditions, the collector currents IQ1 and IQ2 are equal, suitably 4µA, so that amplifier 10 neither sinks nor supplies a difference current IL at output terminal 20. Under load conditions, output stage 18 responds to Vin by imbalancing the collector currents so that together transistors Q1 and Q2 source load current IL to load 22 so that Vo follows Vin. Alternately, if load 22 was connected to Vcc instead of Vee, transistors Q1 and Q2 would sink current from the load.

Drive voltage Vd is applied to the base 42 of a 1x npn control transistor Q3 whose collector 44 is connected to Vcc and conducts a control current Ic and whose emitter 46 is connected to the base 48 of output transistor Q2. Transistors Q2 and Q3 set the reference voltage for Vd at two base-emitter voltages above Vee. Control transistor Q3 responds to variations in Vd by adjusting the voltage at base 48 of transistor Q2, which changes its collector current IQ2. This imbalances the output transistors' collector currents and adjusts load current IL. Because the change in voltage at base 48 of transistor Q2 is the same as the change in drive voltage Vd, the gain provided by transistor Q2 alone is relatively small.

A 1x npn gain transistor Q4 has an emitter 50 that is connected to the emitter 46 of control transistor Q3 for the purpose of sensing changes in Vd. A voltage source Vref clamps the voltage at base 52 of transistor Q4 at two base-emitter voltages above Vee so that at balance Vd and Vref are the same and under load conditions Vd is less than Vref. Therefore, gain transiator Q4 and output transistor Q2 respond to a change in Vd by adjusting their base-emitter voltages by equal but opposite amounts. Transistor Q4 responds to changes in its base-emitter voltage by adjusting a gain current Ig that flows through its collector 54.

A regenerative current source 55 includes a current mirror CM1 that mirrors gain Ig from collector 54 of gain transistor Q4 to a current limiter 58, which in turn supplies current Isup to emitter 50 of gain transistor Q4. Current mirror CM1 includes a diode D1 that is connected across the base-emitter junction of a 1x pnp transistor Q5. The base/collector 56 of diode D1 is connected to collector 54, and the collector 57 of transistor Q5 is connected to current limiter 58. A constant current source IS1 injects current Is1, suitably 1µA, into the signal path at collector 57 to increase the amount of current Ilim= (Ig+Is1) that is supplied to current limiter 58. During normal operation, current limiter 58 multiplies the current Ilim by a constant factor greater than one, suitably 1.5, and supplies it as current Isup to emitters 50 and 40 of gain and control transistors Q4 and Q3.

If drive voltage Vd is reduced too much, control transistor Q3 turns off so that all of the regenerated current is supplied to gain transistor Q4. Because the signal path has a gain greater than one, gain current Ig if left unchecked would increase without bound and destroy the amplifier. Therefore, current limiter 58 responds to large gain currents Ig by reducing its gain and eventually shutting down to prevent the amplifier from destroying itself.

Current limiter 58 is preferably a current peaking circuit that includes a 1x npn transistor Q6 having an emitter 59 that is tied to Vee, a base 60 that is connected to collector 57 of transistor Q5, and a collector 61. A resistor R5, suitably 100 ohms, is connected between base 60 and collector 61. A 1.5x npn transistor Q7 has an emitter 62 that is connected to Vee, a base 63 that is tied to collector 61 of transistor Q6, and a collector 64 that is returned to emitter 50 of gain transistor Q4. When gain current Ig is small the voltage across resistor R5 is very small so that transistors Q6 and Q7 act like a current mirror with a gain of 1.5 to supply Ig to gain transistor Q4. As Ig increases, the base-emitter voltage of transistor Q6 increases logarithmically which tends to cause transistor Q7 to increase Isup. However, the voltage across resistor R5 increases linearly and drives the voltage at collector 61 of transistor Q6 towards Vee which tends to reduce Isup. Thus, current limiter 58 begins to limit at the point where the voltage across resistor R5 increases faster than the base-emitter voltage of transistor Q6. This reduces the base voltage at transistor Q7, which limits current Ig.

The regenerative feedback loop is described by a pair of equations that must be satisfied to stabilize output stage 18. The currents summed at emitter 46 of control transistor Q3, ignoring the base current of transistor Q2 and assuming that the emitter currents of transistors Q3 and Q4 equal their respective collector currents Ic and Ig, satisfy: Isup = Ic + Ig The current Isup supplied by current limiter 58 is described by the following feedback equation: Isup = G(Ig+Is1) where G is the gain of current limiter 58, suitably 1.5 during normal operation and progressively smaller as limiting occurs.

At balance, current limiter 58 preferably supplies 3µA of current (Isup=3µA), which is split between transistors Q3 and Q4 so that Ic=2µA and Ig=1µA. These values satisfy both equations 1 and 2 so that amplifier 10 is stable. Under load conditions, gain transistor Q4 responds to changes in its base-emitter voltage by adjusting Ig. Regenerative current source 55 senses the change in Ig and adjusts Isup to supply the required gain current. Control transistor Q3 absorbs any excess current supplied by the regenerative process by adjusting Ic so that equations 1 and 2 are again satisfied.

A current controlled voltage element 65 is connected between current mirror CM1 and Vcc so that the current (2Ig) drawn from the positive supply to supply current mirror CM1 flows through voltage element 65. Thus, twice the gain current Ig modulates a control voltage Vc at the base 66 of output transistor Q1. Control voltage Vc moves in the same direction as the voltage applied to base 48 of output transistor Q2. Therefore, transistor Q1 adjusts its collector current IQ1 in opposition to the change in collector current IQ2, which further imbalances output stage 18 and increases drive current IL.

Voltage element 65 includes a diode D2, which is implemented as a diode connected 5x pnp transistor, whose base/collector 67 is connected to base 66 of output transistor Q1 and the input of current mirror CM1. A resistor R6, suitably 2.9K, is connected between Vcc and D2's emitter 68. Thus, the base-emitter voltage across output transistor Q1 is the sum of the voltages across resistor R6 and diode D2, which increase linearly and logarithmically, respectively, as gain current Ig increases.

At balance, the voltages across resistor R6 and diode D2 are approximately 5.8mV and 0.7V, respectively. Therefore, the diode voltage dominates and the resistor voltage can be ignored. As a result, voltage element 65 mirrors Ig with a fixed amount of gain to output transistor Q1 so that its collector current IQ1 is proportional to gain current Ig.

However, as gain current Ig increases the voltage drop across resistor R6 becomes progressively more significant, and at some point the change in control voltage Vc becomes approximately linear. Output transistor Q1 responds to a linear change in base-emitter voltage by adjusting its collector current IQ1 as an approximately exponential function of gain current Ig.

The effect of this is that output transistor Q1 sources a lot more current to load 22 for a given change in drive voltage Vd than output transistor Q2 sinks for an equivalent opposite change in Vd. Thus, output stage 18 responds asymmetrically to changes in drive voltage Vd and only provides high gain when sourcing current to the load. Thus, the load is preferably connected to low supply Vee so that output stage 18 never sinks current. Alternately, the high gain output transistor could be used to sink current, in which case the load would be connected to Vcc. In practice, the nonlinear gain does not matter unless the amplifier is being used for a special application that requires gain linearity. Furthermore, the benefits of reduced no load idle current outweigh the minimal effects of gain nonlinearity.

FIGs. 3a, 3b and 3c are together a schematic diagram of a preferred embodiment of amplifier 10 shown in FIG. 1. The preferred input stage 12 is similar to those used in operational amplifiers OP-284 and OP-291 produced by Analog Devices, Inc., the assignee of the present invention. Input circuit 28 comprises a pair of 2x pnp transistors Q8 and Q9 whose bases 69 and 70 provide the non-inverting and inverting inputs 24 and 26, respectively. Their collectors 72 and 74 are connected to Vee. A pair of 2x npn transistors Q10 and Q11 have bases 76 and 78 that are tied together at node 80, and emitters 82 and 84 that are connected to the respective emitters 86 and 87 of transistors Q8 and Q9. The collectors 88 and 89 of transistors Q10 and Q11 are connected to resistors R1 and R2 and conduct input currents Ilow+ and Ilow-, respectively.

A pair of diodes D3 and D4, which are implemented as diode connected 1x npn transistors, are connected between node 80 and respective emitters 82 and 84 of transistors Q10 and Q11. Thus, currents Ilow+ and Ilow- in transistors Q10 and Q11 are twice the currents in D3 and D4, respectively. A current source IS2 supplies current Is2, suitably 1.5µA, to node 80 to supply transistors Q10 and Q11, and diodes D3 and D4.

At balance, supply current Is2 is split equally between the two sides of differential input circuit 28 so that Ilow+ and Ilow- conduct 1.5µA. Input circuit 28 responds to a relative increase in Vin at the base 69 of transistor Q8 (non-inverting terminal 24) by reducing and increasing the voltages across diodes D3 and D4, respectively, so that a smaller portion of Is2 flows through diode D3 and a larger portion flows through diode D4. The changes in diode current are reflected into Ilow+ and Ilow-.

The topology of input circuit 28 allows Vin to swing from the low supply voltage Vee to within two base-emitter voltages of positive supply voltage Vcc. The base-collector voltages of transistors Q8 and Q9 can operate effectively with zero volts. Therefore, Vin can include Vee without turning input circuit 28 off. Conversely, if Vin rises to within two base-emitter voltages of Vcc, the transistors begin turning off.

The input stage's dual input circuits 28 and 30 are identical except for the reversed conductivities of their transistors and diodes, and thus a detailed description of input circuit 30 is omitted. In general, input circuit 30 includes a pair of npn transistors Q12 and Q13 whose bases are tied to the non-inverting and inverting terminals, respectively. A current source IS3 draws a reference current from a pair of diodes D5 and D6. The diodes are connected across the base-emitter junctions of pnp transistors Q14 and Q15, and respond to changes in Vin to modulate their collector currents Ihigh+ and Ihigh- which flow through resistors R3 and R4, respectively.

The preferred transimpedance stage 14 is the folded cascode circuit used in opamp OP-284 produced by Analog Devices, Inc. The folded cascode circuit comprises a pair of 2x pnp transistors Q16 and Q17 having bases 90 and 92 that are connected together at node 94, and emitters 96 and 98 that are connected to resistors R1 and R2 and conduct currents I1 and I2, respectively. A current source IS4 draws a bias current Is4, suitably 0.5µA, from node 94. A pair of 2x npn transistors Q18 and Q19 have bases 100 and 102 that are connected together at node 104, and emitters 106 and 108 that are connected to resistors R3 and R4 and conduct currents I3 and I4, respectively. The collectors 110 and 112 of transistors Q16 and Q18 are connected together and conduct the same current, I3=I1. The collectors 114 and 116 of transistors Q17 and Q19 are connected at gain node 16 and together source current at gain node 16 in response to changes in Vin.

The folded cascode circuit establishes a constant voltage drop across resistors R1 and R2, suitably 50K, by fixing the voltage at node 94. A resistor R7, suitably 45K, is connected between Vcc and the emitter 118 of a diode D7, which is implemented as a diode connected 1.5x pnp transistor, whose base/collector 120 is connected to node 94. Diode D7 and resistor R7 are biased so that the voltages across resistors R1 and R2 are approximately the same as the voltage across R7. As a result, 4.5µA of continuous current flows through resistors R1 and R2.

The folded cascode circuit uses a 1x npn transistor Q20 to control transistor Q18 and force I3 to be substantially the same as I1. The base 122 of transistor Q20 is connected to collector 110, its collector 124 is connected to node 94, and its emitter 126 is connected to node 104. If I3 falls below I1, current is driven into base 122 of Q20. This pulls up base 100 of Q18 so that it increases I3. Conversely, if I3 rises above I1, the base drive to Q20 is reduced. This pulls base 100 of Q18 down, which in turn reduces I3.

The result is that the folded cascode circuit drives current I3 through resistor R3, which together with current Ihigh+ from input circuit 30 set the voltage across R3. Currents I3 and Ihigh+ respond to changes in Vin by moving in the same direction so that the voltage across R3 reflects that change. The voltage at base 100 of Q18, and hence the voltage at base 102 of Q19 move up and down with the voltage across R3 to keep I3 the same as I1. Transistor Q19 responds to variations of its base voltage by adjusting I4 so that the voltage across R4 tries to follow the voltage across R3.

At balance, I1 = I2 = 3µA and Ihigh+ = Ihigh- = 1.5µA. Since the folded cascode circuit forces I3 to equal I1, I3 is also 3µA. Thus, transistor Q19 supplies I4 at 3µA so that the voltages across resistors R3 and R4 are equal. Because currents I2 and I4 are equal, drive voltage Vd at gain node 16 remains at its reference value and the drive current provided to the next stage is unchanged.

Under load conditions, amplifier 10 reduces Vd relative to its reference voltage so that output stage supplies load current to hold Vo at Vin. Amplifier 10 responds to an increase in Vin by increasing Ihigh+ and I1, and hence I3, and reducing I2 and Ihigh-. This increases the voltage across resistor R3, which in turn increases the voltage at base 102 of transistor Q19. As the voltage across resistor R3 is increased, the voltage across resistor R4 that is attributable to Ihigh- is reduced. Thus, transistor Q19 increases I4 to pull up the voltage across resistor R4. This pulls the voltage at its collector 116 and at gain node 16 down thereby reducing drive voltage Vd and reducing the drive current. Amplifier 10 responds to a reduction in Vin by increasing drive voltage Vd and increasing the drive current at gain node 16.

Buffer circuit 32 is connected between gain node 16 and base 42 of control transistor Q3 in output stage 18. The primary purpose of buffer circuit 32 is to establish a voltage drop equal to the voltage across resistor R3 at balance between collector 116 of transistor Q19 and base 42 of control transistor Q3. This keeps the voltages at the collectors 112 and 116 of transistors Q18 and Q19 approximately equal, which lowers the amplifier's offset voltage. A secondary purpose is to buffer gain node 16 from base 42 of control transistor Q3 so that the change in base current does not have to be provided entirely by transimpedance stage 14.

Buffer circuit 32 includes a 1x npn transistor Q21 having a base 128 that is connected to gain node 16, a collector 130, and an emitter 132 that is connected to one side of a resistor R8. A diode D8, implemented as a 1x diode connected npn transistor, has a base/collector 134 that is connected to base 42 of control transistor Q3 and an emitter 136 that is connected to the other side of resistor R8. Transistor Q21 and diode D8 are biased so that the voltage drop across resistor R8 is approximately equal to the voltage across resistor R3 at balance.

A current mirror CM2 mirrors the collector current in transistor Q21 to the base/collector 134 of diode D8 to provide the base current that drives control transistor Q3. Therefore, a change in base current at transistor Q3 of ΔI only requires a change in drive current at gain node 16 of ΔIβ where β is the current gain of transistor Q21. Current mirror CM2 includes a diode D9, implemented as a diode connected 1x pnp transistor, and a 1x pnp transistor Q22. The emitters 138 and 140 of diode D9 and transistor Q22, respectively, are connected to resistor R7 to draw supply current from Vcc. (This also provides the bias current that sets the voltage across resistor R7). The base/collector 142 of diode D9 is connected to the collector 130 of transistor Q21 and to the base 144 of transistor Q22. Transistor Q22's collector 146 is connected to base/collector 134 of diode D8.

As described above in FIG. 2, output stage 18 responds to drive signal Vd by supplying load current IL at output terminal 20 to an external load thereby modulating its output voltage Vo between ground and 5V. Regenerative current source 55 supplies gain current Ig as needed to respond to changes in drive voltage Vd and provide the desired gain. When amplifier 10 is idling, either because input voltage signal Vin is not being applied or because the signal pauses momentarily, regenerative current source 55 supplies only a minimal amount of gain current. This lowers the power consumption of amplifier 10 without sacrificing performance. This saves money, lengthens the life of amplifier 10, and reduces the physical dimensions of the amplifier IC.

Amplifier 10 uses a single bias circuit 148 to establish the reference voltage level at the base 52 of transistor Q4 in output stage 18, supply current to buffer circuit 32 and resistor R7, and supply current for diode D7. This is done to conserve current and lower the amplifier's power consumption during idle periods.

A current source IS5 supplies bias current Is5, suitably 2µA, that flows from high supply Vcc, through 2x diodes D10 and D11 and into Vee. The base/collector 150 of diode D10 is connected to base 52 of transistor Q4. This sets the base voltage at two base-emitter voltages above the low supply Vee. The base/collector 152 of diode D11 is connected to the bases 154 and 156 of transistors Q23 and Q24, respectively. Their emitters 158 and 160 are connected to Vee.

Transistor Q23 has an emitter area of 3x, and thus supplies 3µA of current. This current is split equally between transistor Q21 and diode D8. Transistor Q24 has. an emitter area of 1.5x, and thus supplies 1.5µA of current that is drawn from high supply Vcc through resistor R7, diode D7, transistor Q20, and into its collector 162.

Amplifier 10 conserves current and thus lowers power consumption by recycling the bias currents for use in multiple parts of the amplifier. However, sustained extreme inputs could cause amplifier 10 to self-destruct. To prevent this, a pair of clamps QC1 and QC2 are added to the folded cascode circuit, and a current limiter QL1 is added to output stage 18.

Clamp QC1 is a 1x npn transistor having a base 164 that is connected to transistor Q18's collector 112, a collector 166 that is connected to Vcc, and an emitter 168 that is connected to transistor Q19's collector 116. In normal operation, the voltages at collectors 112 and 116 are approximately the same so that QC1 is turned off. However, if transistor Q19's collector voltage drops too much, QC1 turns on, which pulls Q19 up and prevents it from saturating.

Clamp QC2 is a 1x npn transistor having a base 170 that is connected to emitter 136 of diode D8, a collector 172 that is tied to Vcc, and an emitter 174 that is connected to collector 162 of transistor Q24. In normal operation QC2 is turned off. However, if transistor Q17's voltage pulls up too much, it may saturate. This pulls up base 170 of clamp QC2, which turns it on. Thus, the current supplied by transistor Q24 is provided to clamp QC2 instead of diode D7. This turns the folded cascode circuit off until input voltage Vin is reduced.

Current limiter QL1 includes a 1x pnp transistor Q25 having a base 176 that is connected to collector 44 of control transistor Q3, an emitter 178 that is tied to Vcc, and a collector 180 that is connected to collector 130 of buffer transistor Q21. A resistor R9 is connected across the base-emitter junction of transistor Q25. In normal operation, transistor Q25 is off. However, if drive voltage Vd, and hence the voltage at base 42 of control transistor Q3 is increased too much, transistor Q25 will turn on and supply the collector current for transistor Q21. This reduces the current in current mirror CM2 which in turn reduces the base drive to transistor Q3 and increases its base voltage.

Amplifier 10 uses four capacitors C1-C4 to control its frequency response. Capacitor C1, suitably 15pF, is connected between output terminal 20 and gain node 16. C1 is the primary compensation capacitor and serves three functions. First, C1 provides local negative feedback from the output of the amplifier back to base 42 of control transistor Q3. C1 also provides pole splitting that drives the low and high frequency poles of the amplifier outside its frequency range. Finally, C1 controls the amplifier's slew rate. Capacitor C2 is connected from transistor Q18's collector 112 to Vee. C2 reduces the high frequency transconductance of the folded cascode circuit and limits the amplifier's bandwidth. Capacitor C3 is connected between gain node 16 and base/collector 134 of diode D8. C3 stabilizes the amplifier by compensating for the parasitic capacitance at the collector of Q23. Capacitor C4 is connected between gain node 16 and emitter 46 of control transistor Q3. C4 prevents the amplifier from oscillating.

While several illustrative embodiments of the invention have been shown and described, numerous variations and alternate embodiment will occur to those skilled in the art. For example, different input and transimpedance stages could be used with the output stage of the present invention. Such variations and alternate embodiments are contemplated, and can be made without departing from the scope of the invention as defined in the appended claims.


Anspruch[de]
  1. Verstärkerausgangsstufe, die aufweist:
    • einen ersten und einen zweiten Versorgungsspannungsanschluss (Vcc, Vee);
    • einen Ausgangsanschluss (20) zur Verbindung mit einer externen Last (22);
    • einen ersten und einen zweiten Ausgangstransistor (Q1, Q2) entgegengesetzter Leitfähigkeiten, die Basen (66, 48), Kollektoren (38, 40), die an dem Ausgangsanschluss verbunden sind, und Emitter (34, 36), die jeweils mit dem ersten und dem zweiten Versorgungsspannungsanschluss verbunden sind, so dass die Transistoren jeweilige Ausgangsströme (IQ1, IQ2) leiten, die einen Laststrom (IL) an dem Ausgangsanschluss erzeugen, haben; einen Verstärkungstransistor (Q4), der eine Basis (52), die bei einer Referenzspannung gehalten wird, einen Emitter (50) und einen Kollektor (54), der einen Verstärkungsstrom (Ig) leitet, der sich über einen vorbestimmten Bereich variiert, besitzt;
    • eine regenerative Stromquelle (55), die einen Strom zu dem Verstärkungstransistor durch Rückführen des Verstärkungsstroms in einem regenerativen Rückführungspfad (CM1, IS1, 58) zu seinem Emitter zuführt, so dass die Stromquelle einen Nicht-Last-Ruhestrom nahe einem unteren Ende des vorbestimmten Bereichs zuführt und in der Lage ist, einen Verstärkungsstrom über diesen Bereich zuzuführen;
    • ein Spannungselement (65), das auf den Verstärkungsstrom durch Anlegen einer Steuerspannung zu der Basis des zweiten Ausgangstransistors anspricht, so dass sein Ausgangsstrom als eine ungefähr exponentielle Funktion des Verstärkungsstroms variiert; einen Steuertransistor (Q3), der eine Basis (42), einen Kollektor (44) und einen Emitter (46) besitzt, der mit der Basis des ersten Ausgangstransistors und dem Emitter des Verstärkungstransistors verbunden ist, und einen Steuerstrom (Ic) leitet, der den Rückführpfad stabilisiert, wobei der Steuertransistor auf ein Steuerspannungssignal (Vd) anspricht, angelegt an seine Basis, durch Modulieren der Basis-Emitter-Spannungen des ersten Ausgangs und von Verstärkungstransistoren in entgegengesetzten Richtungen, so dass die Ausgangsströme nicht ausbalanciert sind, um dadurch den Laststrom an dem Ausgangsanschluss zu erzeugen.
  2. Ausgangsstufe nach Anspruch 1, wobei das Spannungselement aufweist:
    • einen Widerstand (R6); und
    • eine Diode (D2), die in Reihe mit dem Widerstand zwischen dem zweiten Versorgungsspannungsanschluss und der Basis des zweiten Ausgangstransistors verbunden ist, so dass ein Biasstrom, der proportional zu dem Verstärkungsstrom ist, dort hindurch fließt und die Steuerspannung als die Summe der Spannungen über den Widerstand und die Diode einstellt,
    wobei das Spannungselement auf Verstärkungsströme in einem unteren Bereich des Bereichs durch Modulieren der Steuerspannung ungefähr logarithmisch anspricht, so dass der Ausgangsstrom des zweiten Transistors ungefähr proportional zu dem Verstärkungsstrom ist, und auf Verstärkungsströme in einem oberen Bereich des Bereichs durch Modulieren der Steuerspannung ungefähr linear anspricht, so dass der Ausgangsstrom des zweiten Transistors ungefähr die exponentielle Funktion des Verstärkungsstroms ist.
  3. Ausgangsstufe nach den Ansprüchen 1 oder 2, wobei die regenerative Stromquelle aufweist:
    • einen Stromspiegel (CM1), der eine erste Seite besitzt, die mit dem Kollektor des Verstärkungstransistors verbunden ist und den Verstärkungsstrom zu einer zweiten Seite spiegelt, und einen Eingang, der ungefähr zweimal den Verstärkungsstrom von dem Spannungselement zieht;
    • eine Stromquelle (IS1), die einen Biasstrom zu dem Verstärkungsstrom an der zweiten Seite des Stromspiegels hinzufügt; und
    • eine Strombegrenzungsschaltung (58), die zwischen der zweiten Seite des Stromspiegels und dem Emitter des Verstärkungstransistors verbunden ist, wobei die Strombegrenzungsschaltung auf eine Erhöhung in dem Verstärkungsstrom durch progressives Verringern der Verstärkung des regenerativen Rückführpfads so anspricht, dass der Verstärkungsstrom, zugeführt durch die regenerative Stromquelle, auf einen maximalen Wert begrenzt wird.
  4. Ausgangsstufe nach Anspruch 3, wobei die Strombegrenzungsschaltung aufweist:
    • einen Begrenzungstransistor (Q6), der eine Basis, die mit der zweiten Seite des Stromspiegels verbunden ist, einen Kollektor und einen Emitter, der mit dem ersten Versorgungsspannungsanschluss verbunden ist, besitzt;
    • einen Versorgungstransistor (Q7), der eine Basis, die mit dem Kollektor des Begrenzungstransistors verbunden ist, einen Kollektor, der mit dem Emitter des Verstärkungstransistors verbunden ist, und einen Emitter, der mit dem ersten Versorgungsspannungsanschluss verbunden ist, besitzt; und
    • einen Begrenzungswiderstand (R5), der zwischen der Basis und dem Kollektor des Begrenzungstransistors verbunden ist, so dass dann, wenn sich der Verstärkungsstrom erhöht, die Spannung an der Basis des Versorgungstransistors zu der ersten Versorgungsspannung hin gesteuert wird, was bewirkt, dass der Versorgungstransistor den Strom, zugeführt zu dem Verstärkungstransistor und dem Steuertransistor, begrenzt.
  5. Ausgangsstufe nach Anspruch 4, wobei der Begrenzungs- und der Versorgungstransistor Emitterbereiche haben, wobei der Emitterbereich des Versorgungstransistors größer als derjenige des Begrenzungstransistors ist.
  6. Ausgangsstufe nach den Ansprüchen 1, 2 oder 3, die weiterhin einen Kondensator (C1) aufweist, der zwischen dem Ausgangsanschluss und der Basis des Steuertransistors verbunden ist, um eine negative Rückführung zu schaffen, um die Ausgangsstufe zu stabilisieren.
  7. Verfahren zum Steuern einer bipolaren Ausgangsstufe (18), die einen ersten und einen zweiten Ausgangstransistor (Q1, Q2), von entgegengesetzten Leitfähigkeiten, aufweist, die Basen, Emitter, die jeweils mit dem ersten und dem zweiten Versorgungsspannungsanschluss (Vcc, Vee) verbunden sind, und Kollektoren, die an einem Ausgangsanschluss (20) verbunden sind, und jeweilige Ausgangsströme leiten, aufweisen, wobei das Verfahren umfasst:
    • Verbinden einer Last (22) zwischen dem Ausgangsanschluss und dem ersten Versorgungsspannungsanschluss;
    • Anlegen eines Steuerspannungssignals an die Basis des ersten Ausgangstransistors, um seinen Ausgangsstrom einzustellen, um dadurch die Ausgangsströme nicht auszubalancieren und einen Laststrom (IL) an dem Ausgangsanschluss zu erzeugen;
    • Erzeugen eines Verstärkungsstroms (Ig) in Abhängigkeit von dem Steuerspannungssignal; Zuführen des Verstärkungsstroms durch Führen von diesem zurück in einem regenerativen Rückführpfad, so dass der Verstärkungsstrom über einen vorbestimmten Bereich variieren kann, während er an einem unteren Ende des Bereichs ruht; und
    • Modulieren einer Steuerspannung (Vc) an der Basis des zweiten Ausgangstransistors als eine ungefähre lineare Funktion des Verstärkungsstroms, so dass sein Ausgangsstrom ungefähr eine exponentielle Funktion des Verstärkungsstroms ist, um dadurch weiterhin die Ausgangsströme nicht auszubalancieren, um die Verstärkung des Laststroms zu erhöhen.
  8. Verfahren nach Anspruch 7, wobei das Zuführen des Verstärkungsstroms aufweist:
    • Spiegeln (CM1) des Verstärkungsstroms in den regenerativen Rückführpfad hinein; Injizieren eines Stroms (IS1) in den regenerativen Rückführpfad hinein, um den Verstärkungsstrom zu erhöhen;
    • Zurückführen (58) des erhöhten Verstärkungsstroms, um den Verstärkungsstrom zuzuführen; und
    • Einstellen eines Steuerstroms, um einen übermäßigen Verstärkungsstrom zu absorbieren und um den regenerativen Rückführpfad zu stabilisieren.
  9. Verfahren nach Anspruch 7 oder 8, wobei ein Rückführen des erhöhten Verstärkungsstroms aufweist:
    • Multiplizieren des erhöhten Verstärkungsstroms mit einem erwünschten Verstärkungsfaktor, wobei der Verstärkungsfaktor einen Wert größer als einer für Verstärkungsströme an einem unteren Ende des vorbestimmten Bereichs besitzt; und
    • progressives Reduzieren des Verstärkungsfaktors, wenn sich der Verstärkungsstrom erhöht, um dadurch die Menge des Verstärkungsstroms, die zugeführt ist, auf weniger als einen maximalen Wert zu begrenzen.
  10. Verfahren nach den Ansprüchen 7, 8 oder 9, wobei ein Modulieren der Steuerspannung aufweist:
    • Einstellen einer ersten Spannung als eine logarithmische Funktion des Verstärkungsstroms;
    • Einstellen einer zweiten Spannung als eine lineare Funktion des Verstärkungsstroms; Summieren der ersten und der zweiten Spannung, um die Steuerspannung an der Basis des zweiten Ausgangstransistors zu liefern, so dass sich die Steuerspannung ungefähr logarithmisch für einen Verstärkungsstrom an einem niedrigeren Ende des Bereichs ändert und sich progressiv stärker linear ändert, wenn sich der Verstärkungsstrom erhöht.
Anspruch[en]
  1. An amplifier output stage, comprising:
    • first and second supply voltage terminals (Vcc, Vee);
    • an output terminal (20) for connection to an external load (22);
    • first and second output transistors (Q1, Q2) of opposite conductivities having bases (66,48), collectors (38,40) that are connected at said output terminal and emitters (34,36)) that are respectively connected to said first and second supply voltage terminals so that said transistors conduct respective output currents (IQ1, IQ2) that produce a load current (IL) at said output terminal;
    • a gain transistor (Q4) having a base (52) that is held at a reference voltage, an emitter (50) and a collector (54) that conducts a gain current (Ig) that varies over a predetermined range;
    • a regenerative current source (55) that supplies current to said gain transistor by returning said gain current in a regenerative feedback path (CM1, IS1, 58) to its emitter so that the current source supplies a no load idle current near a lower end of said predetermined range and is capable of supplying gain current over said range;
    • a voltage element (65) that responds to said gain current by applying a control voltage to the base of the second output transistor so that its output current varies as an approximately exponential function of said gain current;
    • a control transistor (Q3) having a base (42), a collector (44) and an emitter (46) that is connected to the base of said first output transistor and the emitter of said gain transistor and conducts a control current (Ic) that stabilizes the feedback path, said control transistor responding to a drive voltage signal (Vd) applied to its base by modulating the base-emitter voltages of said first output and gain transistors in opposite directions so that said output currents are unbalanced thereby generating said load current at said output terminal.
  2. The output stage of claim 1, wherein said voltage element comprises:
    • a resistor (R6); and
    • a diode (D2) that is connected in series with said resistor between said second supply voltage terminal and the base of said second output transistor so that a bias current that is proportional to said gain current flows therethrough and sets the control voltage as the sum of the voltages across the resistor and the diode,
    • said voltage element responding to gain currents in a lower portion of said range by modulating the control voltage approximately logarithmically so that said second transistor's output current is approximately proportional to said gain current and responding to gain currents in an upper portion of said range by modulating the control voltage approximately linearly so that said second transistor's output current is approximately said exponential function of said gain current.
  3. The output stage of claims 1 or 2, wherein said regenerative current source comprises:
    • a current mirror (Cml) having a first side that is connected to the collector of said gain transistor and mirrors said gain current to a second side, and an input that draws approximately two times said gain current from said voltage element;
    • a current source (IS1) that adds a bias current to the gain current at the second side of the current mirror; and
    • a current limiting circuit (58) that is connected between the second side of the current mirror and the emitter of said gain transistor, said current limiting circuit responding to an increase in gain current by progressively reducing the gain of said regenerative feedback path so that the gain current supplied by the regenerative current source is limited to a maximum value.
  4. The output stage of claim 3, wherein said current limiting circuit comprises:
    • a limiting transistor (Q6) having a base that is connected to the second side of the current mirror, a collector and an emitter that is connected to the first supply voltage terminal;
    • a supply transistor (Q7) having a base that is connected to the limiting transistor's collector, a collector that is connected to the emitter of said gain transistor, and an emitter that is connected to the first supply voltage terminal; and
    • a limiting resistor (R5) that is connected between the base and the collector of said limiting transistor so that as said gain current increases the voltage at the base of said supply transistor is driven towards the first supply voltage which causes the supply transistor to limit the current supplied to the gain and control transistors.
  5. The output stage of claim 4, wherein said limiting and supply transistors have emitter areas, the emitter area of said supply transistor being larger than that of said limiting transistor.
  6. The output stage of claims 1,2 or 3, further comprising a capacitor (C1) that is connected between said output terminal and the base of the control transistor to provide negative feedback to stabilize the output stage.
  7. A method for controlling a bipolar output stage (18) that comprises first and second output transistors (Q1,Q2) of opposite conductivities having bases, emitters that are respectively connected to first and second supply voltage terminals (Vcc,Vee), and collectors that are connected at an output terminal (20) and conduct respective output currents, the method comprising:
    • connecting a load (22) between said output terminal and said first supply voltage terminal;
    • applying a drive voltage signal to the base of said first output transistor to adjust its output current thereby imbalancing said output currents and producing a load current (IL) at said output terminal;
    • generating a gain current (Ig) in response to said drive voltage signal;
    • supplying said gain current by feeding it back in a regenerative feedback path so that said gain current can vary over a predetermined range while idling at a lower end of said range; and
    • modulating a control voltage (Vc) at the base of said second output transistor as an approximately linear function of said gain current so that its output current is approximately an exponential function of said gain current thereby further imbalancing said output currents to increase the gain of said load current.
  8. The method of claim 7, wherein supplying said gain current comprises:
    • mirroring (CM1) said gain current into said regenerative feedback path;
    • injecting current (IS1) into said regenerative feedback path to increase said gain current;
    • returning (58) said increased gain current to supply said gain current; and
    • adjusting a control current to absorb excess gain current and stabilize said regenerative feedback path.
  9. The method of claims 7 or 8, wherein returning said increased gain current comprises:
    • multiplying said increased gain current by a desired gain factor, said gain factor having a value greater than one for gain currents at a lower end of said predetermined range; and
    • progressively reducing said gain factor as said gain current increases thereby limiting the amount of gain current supplied to less than a maximum value.
  10. The method of claims 7,8 or 9, wherein modulating said control voltage comprises:
    • adjusting a first voltage as a logarithmic function of said gain current;
    • adjusting a second voltage as a linear function of said gain current;
    • summing said first and second voltages to provide said control voltage at the base of said second output transistor so that said control voltage changes approximately logarithmically for gain current at a lower end of said range and changes progressively more linearly as said gain current increases.
Anspruch[fr]
  1. Etage de sortie d'amplificateur, comprenant :
    • des première et deuxième bornes (Vcc, Vee) de tension d'alimentation ;
    • une borne de sortie (20) pour une connexion à une charge extérieure (22) ;
    • des premier et deuxième transistors de sortie (Q1, Q2) de conductivités opposées ayant des bases (66, 48), des collecteurs (38, 40) qui sont connectés à ladite borne de sortie et des émetteurs (34, 36) qui sont respectivement connectés auxdites première et deuxième bornes de tension d'alimentation de telle sorte que lesdits transistors conduisent des courants de sortie respectifs (IQ1, IQ2) qui produisent un courant de charge (IL) à ladite borne de sortie ;
    • un transistor (Q4) de gain ayant une base (52) qui est maintenue à une tension de référence, un émetteur (50) et un collecteur (54) qui conduit un courant (Ig) de gain qui varie dans une plage prédéterminée ;
    • une source de courant à réaction (55) qui applique un courant audit transistor de gain en renvoyant ledit courant de gain dans un trajet de rétroaction positive (CM1, IS1, 58) vers son émetteur de telle sorte que la source de courant applique un courant réactif sans charge près d'une extrémité inférieure de ladite plage prédéterminée et est capable d'appliquer un courant de gain dans ladite plage ;
    • un élément (65) de tension qui répond audit courant de gain par application d'une tension de commande à la base du deuxième transistor de sortie de telle sorte que son courant de sortie varie comme une fonction approximativement exponentielle dudit courant de gain ;
    • un transistor de commande (Q3) ayant une base (42), un collecteur (44) et un émetteur (46) qui est connecté à la base dudit premier transistor de sortie et à l'émetteur dudit transistor de gain et conduit un courant de commande (Ic) qui stabilise le trajet de rétroaction, ledit transistor de commande répondant à un signal de tension d'attaque (Vd) appliqué à sa base par modulation des tensions base-émetteur desdits premiers transistors de sortie et de gain dans des directions opposées de telle sorte que lesdits courants de sortie sont déséquilibrés afin de générer ledit courant de charge à ladite borne de sortie.
  2. Etage de sortie selon la revendication 1, dans lequel ledit élément de tension comprend :
    • une résistance (R6) ; et
    • une diode (D2) qui est connectée en série avec ladite résistance entre ladite deuxième borne de tension d'alimentation et la base dudit deuxième transistor de sortie de telle sorte qu'un courant de polarisation qui est proportionnel audit courant de gain circule dans celui-ci et établit la tension de commande sous la forme de la somme des tensions aux bornes de la résistance et de la diode,
    • ledit élément de tension répondant à des courants de gain dans une partie inférieure de ladite plage par modulation de la tension de commande de manière approximativement logarithmique de telle sorte que ledit deuxième courant de sortie de transistor est approximativement proportionnel audit courant de gain et répondant à des courants de gain dans une partie supérieure de ladite plage par modulation de la tension de commande de manière approximativement linéaire de telle sorte que ledit deuxième courant de sortie de transistor est approximativement ladite fonction exponentielle dudit courant de gain.
  3. Etage de sortie selon les revendications 1 ou 2, dans lequel ladite source de courant à réaction comprend :
    • un miroir de courant (Cm1) ayant un premier côté qui est connecté au collecteur dudit transistor de gain et qui reflète ledit courant de gain vers un deuxième côté, et une entrée qui absorbe approximativement deux fois ledit courant de gain en provenance dudit élément de tension ;
    • une source (IS1) de courant qui ajoute un courant de polarisation au courant de gain au niveau du deuxième côté du miroir de courant ; et
    • un circuit (58) de limitation de courant qui est connecté entre le deuxième côté du miroir de courant et l'émetteur dudit transistor de gain, ledit circuit de limitation de courant répondant à un accroissement du courant de gain en réduisant progressivement le gain dudit trajet de rétroaction positive de telle sorte que le courant de gain appliqué par la source de courant à réaction est limité à une valeur maximum.
  4. Etage de sortie selon la revendication 3, dans lequel ledit circuit de limitation de courant comprend :
    • un transistor de limitation (Q6) ayant une base qui est connectée au deuxième côté du miroir de courant, un collecteur et un émetteur qui est connecté à la première borne de tension d'alimentation ;
    • un transistor d'alimentation (Q7) ayant une base qui est connectée au collecteur du transistor de limitation, un collecteur qui est connecté à l'émetteur dudit transistor de gain, et un émetteur qui est connecté à la première borne de tension d'alimentation ; et
    • une résistance de limitation (R5) qui est connectée entre la base et le collecteur dudit transistor de limitation de telle sorte que lorsque ledit courant de gain croît, la tension à la base dudit transistor d'alimentation est entraînée vers la première tension d'alimentation qui conduit le transistor d'alimentation à limiter le courant appliqué aux transistors de gain et de commande.
  5. Etage de sortie selon la revendication 4, dans lequel lesdits transistors de limitation et d'alimentation ont des zones d'émetteur, la zone d'émetteur dudit transistor d'alimentation étant plus grande que celle dudit transistor de limitation.
  6. Etage de sortie selon les revendications 1, 2 ou 3, comprenant en outre un condensateur (C1) qui est connecté entre ladite borne de sortie et la base du transistor de commande pour obtenir une rétroaction négative pour stabiliser l'étage de sortie.
  7. Procédé pour commander un étage de sortie bipolaire (18) qui comprend des premier et deuxième transistors de sortie (Q1, Q2) de conductivités opposées ayant des bases, des émetteurs qui sont respectivement connectés à des première et deuxième bornes (Vcc, Vee) de tension d'alimentation, et des collecteurs qui sont connectés à une borne de sortie (20) et conduisent des courants de sortie respectifs, le procédé comprenant :
    • la connexion d'une charge (22) entre ladite borne de sortie et ladite première borne de tension d'alimentation ;
    • l'application d'un signal de tension d'attaque à la base dudit premier transistor de sortie pour régler son courant de sortie afin de déséquilibrer lesdits courants de sortie et de produire un courant de charge (IL) à ladite borne de sortie ;
    • la génération d'un courant (Ig) de gain en réponse audit signal de tension d'attaque ;
    • l'application dudit courant de gain par sa ré-introduction dans un trajet de rétroaction positive de telle sorte que ledit courant de gain peut varier dans une plage prédéterminée tout en étant au repos à une extrémité inférieure de ladite plage ; et
    • la modulation d'une tension de commande (Vc) à la base dudit deuxième transistor de sortie comme une fonction approximativement linéaire dudit courant de gain de telle sorte que son courant de sortie est approximativement une fonction exponentielle dudit courant de gain, afin de déséquilibrer encore plus lesdits courants de sortie pour accroître le gain dudit courant de charge.
  8. Procédé selon la revendication 7, dans lequel l'application dudit courant de gain comprend :
    • la réflexion (CM1) dudit courant de gain dans ledit trajet de rétroaction positive ;
    • l'injection d'un courant (IS1) dans ledit trajet de rétroaction positive pour accroître ledit courant de gain ;
    • le renvoi (58) dudit courant de gain accru pour appliquer ledit courant de gain ; et
    • le réglage d'un courant de commande pour absorber un courant de gain en excès et stabiliser ledit trajet de rétroaction positive.
  9. Procédé selon les revendications 7 ou 8, dans lequel le renvoi dudit courant de gain accru comprend :
    • la multiplication dudit courant de gain accru par un facteur de gain souhaité, ledit facteur de gain ayant une valeur supérieure à un pour des courants de gain à une extrémité inférieure de ladite plage prédéterminée ; et
    • la réduction de manière progressive dudit facteur de gain lorsque ledit courant de gain croît, afin de limiter la quantité de courant de gain appliqué à moins d'une valeur maximum.
  10. Procédé selon les revendications 7, 8 ou 9, dans lequel la modulation de ladite tension de commande comprend :
    • le réglage d'une première tension comme une fonction logarithmique dudit courant de gain ;
    • le réglage d'une deuxième tension comme une fonction linéaire dudit courant de gain ;
    • l'addition desdites première et deuxième tensions pour obtenir ladite tension de commande à la base dudit deuxième transistor de sortie de telle sorte que ladite tension de commande varie approximativement de manière logarithmique pour un courant de gain à une extrémité inférieure de ladite plage et varie progressivement plus linéairement lorsque ledit courant de gain croît.






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