PatentDe  


Dokumentenidentifikation EP0881732 27.02.2003
EP-Veröffentlichungsnummer 0881732
Titel Vorrichtung zur Annäherung des Effektivwertes eines Stromes
Anmelder Square D Co., Palatine, Ill., US
Erfinder Phillips, Timothy Brian, Raleigh, North Carolina 27615, US;
Stentz, Antoine Didier, 92500 Rueil-Malmaison, FR
Vertreter derzeit kein Vertreter bestellt
DE-Aktenzeichen 69432057
Vertragsstaaten CH, DE, ES, FR, GB, IT, LI
Sprache des Dokument EN
EP-Anmeldetag 03.08.1994
EP-Aktenzeichen 981129596
EP-Offenlegungsdatum 02.12.1998
EP date of grant 22.01.2003
Veröffentlichungstag im Patentblatt 27.02.2003
IPC-Hauptklasse H02H 3/26
IPC-Nebenklasse G01R 19/02   H02H 3/093   

Beschreibung[en]
Technical Field

Applicant's invention relates generally to the conversion and measurement of the current of an electrical load, and more particularly to an apparatus that will produce a signal proportional to the rms current of the load.

Background Art

Many methods have been utilized to measure the AC current flowing to a load. These methods are used as part of more complex devices such as solid state breakers or overload relays, AC line monitoring devices, or current feedback control loops as required for motor drives and power supplies. The application usually determines the degree of measurement accuracy required. Root-mean-square (rms) current is generally considered to be an accurate representation of the actual current flowing in the circuit being monitored. For simple systems, this may not be necessary and instead, average current over a set time period, usually one cycle, is used to represent the actual current. Other systems will use peak current over the same time period as the basis. More sophisticated microprocessor based devices will actually compute the rms value by sampling the current waveforms many times during each time period, and using those sample measurements to generate the value of the current over the time period.

Using a solid state overload relay as an example of one such application, a common method used to generate a signal representative of the line current is to use a peak detecting circuit as disclosed in commonly assigned U.S. Patent 4,345,288. Although this device provides a close approximation of a standard thermal electromechanical overload unit, the device does not compensate for non-sinusoidal currents that may be encountered in some instances. Likewise, line harmonics and transients may cause erroneous results. An alternative method, as disclosed in French Patent FR2540303 (= US4513342), monitors the squared-time (I2t) value of load current to provide an overload indication, should a predetermined value be exceeded. This Frends Patent discloses an apparatus having the features of the preamble of claim 1. An alterative method using a microprocessor based device is outlined in U.S. Patent 5,220,478 which will compute the rms current through digital sampling techniques. Whereas this is a more accurate method, it is a relatively expensive solution because of the increased component requirements for support circuitry and the increase in the size of the device to house the extra components. For a low cost application where size is also a factor, it would be desirable to provide a solid state overload relay that computes an approximation of the rms current without the complexity of a microprocessor based device.

Summary of Invention

It is an object of the invention to provide improved apparatus for overload protection.

The invention provides an apparatus as defined in the appended claims.

In the preferred embodiment of the invention, conventional current transformers sense the current flow in each phase of load. The load typically could be a single or three phase motor. The current transformers generate an output current. This output is proportional in magnitude to the sensed current. This voltage signal is applied to two circuits connected in parallel, one to measure the peak value of the voltage over one cycle of the applied AC voltage. The outputs of both of these circuits are connected together at a summing junction through different valued resistors of a buffer amplifier. These different resistance values at the input to the summing point serve as to provide different weighting factors to the two signals to produce a composite voltage signal. This signal will be a DC level, which for a sinusoidal current, closely approximates a scaled rms value of the original input load current. For the common non-sinusoidal current waveforms encountered in most applications, this circuit will retain its accuracy to within a+/-5% of the true rms value.

For a current monitoring function, this output can be easily converted and scaled to a digital representation of the load current and visually displayed. To provide an overload or circuit breaker function, this output is fed to a time integrating circuit to produce various trip curves, the output of which is compared with a predetermined trip reference voltage signal. When this output exceeds this level, the overload or breaker will trip, providing an output contact or contacts that will change state when this does occur.

Various power conversation devices such as PWM inverters require a current feedback signal representative of the load current as a controlling element of the device for current limit control. The output voltage of the present invention can provide this function by utilzing this output, with proper scaling factors, as an input to the inverter as the current feedback signal which is proportional to the rms current of the load.

Other features and advantages of the invention, which are believed to be novel and non-obvious, will be apparent from the following specification taken in conjunction with the accompanying drawings in which there is shown a preferred embodiment of the invention. Reference is made to the claims for interpreting the full scope of the invention which is not necessarily represented by such embodiment.

Brief Description of Drawings

  • FIG. 1 is a diagram of a typical prior art solid state overload relay (SSOLR)
  • FIG. 2 is a schematic block diagram of a SSOLR utilizing a system for converting the load current to an approximation of the rms value of the current according to an embodiment of the present invention.
  • FIG. 3 is a detailed schematic block diagram of the approximation circuit as depicted in Fig. 2.

Detailed Description

Although this invention is susceptible to embodiments of many different forms, a preferred embodiment will be described and illustrated in detail herein. The present disclosure exemplifies the principles of the invention and is not to be considered a limit to the broader aspects of the invention to the particular embodiment as described.

FIG. 1 illustrates a typical solid state overload relay protective device representative of prior art. A circuit breaker function would be similar. Three phase incoming power L1-L3 is fed to a load 2. The load could be lighting equipment, heating equipment or inductive loads such as motors, magnets, brakes or coils. Current sensors 4 monitor the load currents L1-L3 to create currents i1-i3 respectively which are proportional in magnitude to the sensed currents. The current sensors 4 generally are current transformers. A current voltage converter 6 transforms the three currents i1-i3 to an output voltage that is proportional to a composite of the sum of the three currents. The resulting voltage Vo is mostly DC with about a 10% ripple for balanced sinusoidal currents. A peak detecting circuit 8. Typically consisting of a diode and a capacitor, will capture the peaks of the ripple voltage Vo to generate a voltage V1 which will be a DC voltage that is proportional to the peak current of the load 2. The overload relay function is time based and not instantaneous. The greater the magnitude of the overload, the faster the overload relay must trip out. Therefore, time integrator amplifier 10 will integrate voltage V1 to create V2 which has an inverse time relationship with the magnitude of the sensed currents l1-l3. Voltage V2 is an exponential response to the input voltage V1. When an overload condition arises, V2 will start ramping up above a level that represents the 100% current rating of the overload relay. To create the overload trip curve a voltage 12, as set by trip level setting circuit 14 is computed such that the output of the time integrator amplifier 10 will reach this voltage level 12 if the overload condition exists for a predetermined amount of time. For instance, if the overload condition is at 600% of the rated load, this time might be set at 10 seconds and be set at 200 seconds if the overload is at 200% of the load. Trip level comparator 16 will compare voltage V2 with this predetermined voltage 4 and will output a signal 18 that will energize control relay 22 through output amplifier 20 once voltage V2 exceeds set level voltage 4. Comparator 16 will function as a schmidt trigger in that once this comparison has been exceeded, the output 18 will remain in the tripped state until output V2 has decayed below a second predetermined reset level 24 and the reset 26 is activated, either manually or automatically. Contacts 28 from relay 22 are used to disconnect the power L1-L3 from the load, the details of which are well known, when the overload relay has tripped.

Referring to Fig.2, an improved solid state overload relay 30 is detailed utilizing a system for converting the load currents L1-L3 to an approximation of the rms value of the current according to the present invention. Although a three phase system is disclosed, it is to be understood that a single phase or polyphase system would function in a similar manner. As discussed above, three phase incoming power L1-L3 is fed to a load 2. Current sensors 4 monitor the load current l1-l3 to create the proportional currents i1-i3, respectively. Each of the currents i1-i3 is independently proceed by an rms current approximation circuit 32-34, the object of the present invention. Current i1 is converted to a voltage V3 by an I-V converter 36. V3, which is proportional to the load current l1, is divided into two paths, one to a peak level detecting circuit 38 and the other to an average level measuring circuit 40. Peak level detecting circuit 38 will capture the peaks of the ripple voltage V3, generating a voltage level V4. Average level measuring circuit 40 generates a voltage V5 which will be a DC voltage that is proportional to the average current of the load 2. V4 and V5 are inputted to scaling and summing amplifier 42 which generates a voltage V6 which is a proportional rms approximation of the sensed line current l1.

It has been empirically determined that an accurate approximation of the line current can be attained based on the equation: Irms = 0.22*pk + 0.766* Iave    where: Irms is the root mean square current,

   Ipk is the peak value of current, and

   Iave is the average value of current.

Scaling and summing amplifier 42 solves this equation to create the DC output voltage V6 which is proportional to rms value of the line currents L1-L3. For most non-sinusoidal current, a +/- 5% accuracy for the approximation can be attained. This compares with a 30% accuracy common for traditional systems based on a peak detecting method.

Likewise, rms current approximation circuits 33 and 34, which are identical with circuit 32, will generate output voltages V7 and V8. The output voltages V6-V8 are fed to an averaging circuit 43 which will combine them to create a composite DC voltage V9 which is proportional to the average of the three rms phase currents l1,l2 and l3. V9 is inputted to time integrator circuit 44 which, along with the trip level comparator 46, and output buffer amplifier 48 provides the timing function and output relay contacts as previously discussed for the overload relay function and is identical with the system disclosed above. For a single phase system, only rms current approximation circuit 32 is required and output voltage V6 is fed directly to the time integrator circuit 44.

For the preferred embodiment of the present invention, Fig. 3 details the approximation circuit 32 as depicted in Fig. 2 which comprises the current to voltage converter 36, the peak level detecting circuit 38. The average level measuring circuit 40, and the scaling and summing amplifier 42. As previously mentioned, approximation circuits 33-34 are identical to circuit 32. Load current L1-L3 are monitored by current transformers in each of the three phase conductors. The secondaries of the current transformers produce current i1-i2 and i3. Currents i1-i3 are reduced in magnitude based on the turns ratio of the current transformers. Each phase current is measured separately by the current to voltage converter circuit 36 in each of the approximation circuits 32-34. Bridge rectifier BR1 produces a full wave recitifed current from i1 to generate a full wave rectified voltage V3 across burden resistor R1. Voltage V3 is divided into two paths, one to peak level detecting circuit 38 through resistor R2 and the other to average level measuring circuit 40 through resistor R3.

The peak detecting circuit 38 consists of a first op amp IC1A, which together with diode D1 combine to form an ideal diode combination and capacitor C2. The ideal diode combination eliminates a voltage drop normally associated with a standard diode which would result in errors in the output voltage V4. Resistor R4 connected in parallel with C2 provides a discharge path with a long time constant to avoid the circuit from becoming just a sample and hold circuit. C2 has low resistance in its charging path and high resistance in its discharge path so that the voltage across C2 will essentially be proportionally equal to the peak value of the input voltage V3. Op amp IC1B provides a buffer for output V4 to avoid the input impedance of the next stage from causing an error in the C2 voltage. The output V4 of buffer amp IB1B thus represents this peak voltage.

A series connected resistor R3 and capacitor C1 combine to form the average level measuring circuit 40. The voltage across C1 will be proportional to the average of the voltage V3. R3 and C1 are scaled to provide this function over the frequency range from 48 Hz to at least 780 Hz. Op amp IC1C provides a buffer for output V5 to avoid the input impedance of the next stage from causing an error in the C1 voltage. The output V5 of buffer amp IC1C thus represents the average of the V3 voltage.

Scaling and summing amplifier circuit 42 receives voltages V4 and V5 at a summing junction of op amp IC1D through resistors R6 and R5 respectively. The values of these resistors along with feedback resistor R7 are calculated such that the output V6 of the summer amplifier IC1D will be proportional to fractions of the each input V4, V5, so as to solve the equation Irms = 0.22*Ipk = 0.766*Iave. Output voltage V6 is a DC voltage which has been empirically determined to be proportional to the rms value of the line currents L1-L3 for sinusoidal currents and having, for most non-sinusoidal currents, an accuracy that is within 5% of the true rms value. For a single phase system, voltage V6 can be directly coupled to time integrated amplifier 44 as disclosed in Fig. 2 to create the improved solid state overload relay previously discussed. For a three phase system, voltage V6 is coupled to the averaging circuit 33 where it is combined with the equivalent voltages V7 and V8 generated by the other two phases to generate the output voltage V9 which is proportional to the average of the three rms phase currents l1-l3. The op amp circuits IC1A-D are supplied from a dual rail +/- 12VDC power supply, not shown, but the details of which are well known.

While the specific embodiments have been illustrated and described, numerous modifications are possible without departing from the scope of the invention. Although in the foregoing embodiments have been applied to single and three phase systems, it will be clearly understood that the invention is equally applicable to polyphase systems, with the requirement being the addition or subtraction of a separate rms approximation circuit for each phase of the voltage source, adjustments in the time constants of the resistor-capitor combinations in the peak level detecting and average level detecting circuit, and changes in the averaging circuit that combines the outputs of the rms approximation circuits.


Anspruch[de]
  1. Halbleiter-Überlastschutzvorrichtung für eine Wechselstromlast (2), die von einer Wechselstromquelle (L1-L3) mit Strom versorgt wird, umfassend
    • a) Mittel (4) zur Erfassung des tatsächlichen, der Last (2) von der Wechselstromquelle (L1-L3) zugeführten Stroms;
    • b) Mittel (36) zur Umwandlung des tatsächlichen Stroms in eine dem tatsächlichen Strom proportionale erste Spannung (V3);
    • c) Mittel (32) zur Erzeugung einer zweiten Spannung aus der ersten Spannung (V3), wobei die zweite Spannung proportional zu einem Näherungswert ist, der gleich dem Effektivstrom der Last (2) ist;
    • d) Mittel (44) zum Integrieren der zweiten Spannung, um ein Auslösesignal (V10) zu erzeugen, das charakteristisch für eine vorbestimmte Volllastkapazität der Wechselstromlast (2) ist;
    • e) Mittel (46) zum Vergleichen des Auslösesignals (V10) mit einem vorbestimmten Auslösereferenzspannungsniveau (12), wobei die Vergleichsmittel (46) ein Ansteuerungs-Ausgangssignal erzeugen, wenn das Auslösesignal (V10) kleiner als das Auslösereferenzspannungsniveau (12) ist und wobei die Vergleichsmittel (46) ein Abschalt-Ansteuerungs-Ausgangssignal erzeugen, wenn das Auslösesignal (V10) größer als das eine Überlastbedingung anzeigende Referenzauslösespannungsniveau (12) ist; und
    • f) Mittel (22), um die Wechselstromquelle als Reaktion auf das Ansteuerungs-Ausgangssignal bei Vorliegen der Überlastbedingung von der Last zu trennen;
    dadurch gekennzeichnet, dass

    die Mittel (32) zur Erzeugung der zweiten Spannung einen Näherungsstromkreis umfassen, wobei der Näherungsstromkreis erste Mittel (40) zur Erzeugung einer Spannung (V5) aus der ersten Spannung (V3), proportional entsprechend einem Mittelwert des tatsächlichen Stromes, zweite Mittel (38) zur Erzeugung einer Spannung aus der ersten Spannung (V3), proportional entsprechend einem Spitzenwert des tatsächlichen Stromes, und dritte Mittel (42) zur Summierung eines Anteils der Spannung des ersten Mittel (40) und eines Anteils der Spannung des zweiten Mittel (38), um die dem Effektivstrom der Last proportionale zweite Spannung (V6) zur erzeugen, aufweist.
  2. Halbieiter-Überlastschutzvorrichtung nach Anspruch 1,

    dadurch gekennzeichnet, dass

    der Näherungsstromkreis eine Näherungsgleichung löst, um das zum Effektivstrom der Last (2) proportionale Ausgangssignal zu erzeugen.
  3. Halbleiter-Überlastschutzvorrichtung nach Anspruch 1 oder 2,

    dadurch gekennzeichnet, dass

    die Näherungsgleichung zur Erzeugung des dem Effektivstrom der Last (2) proportionalen Ausgangsignals der Gleichung Irms = (0.22*Ipk) + (0.766*Iave) entspricht, wobei Irms der Effektivstrom der Last (2), Ipk der Spitzenstrom der Last (2) und Iave der Mittelwert des Stroms der Last (2) sind.
  4. Halbleiter-Überlastschutzvorrichtung nach einem der vorangehenden Ansprüche,

    dadurch gekennzeichnet, dass

    die Wechselstromquelle eine Einphasenquelle ist.
  5. Halbleiter-Überlastschutzvorrichtung nach einem der Ansprüche 1 bis 3,

    dadurch gekennzeichnet, dass

    die Wechselstromquelle eine Mehrphasenquelle ist.
Anspruch[en]
  1. A solid state overload protective apparatus for an AC load(2) supplied power from an AC source (L1 - L3) comprising:
    • a. means (4) to sense actual current supplied to said load (2) from said AC source (L1- L3);
    • b. means (36) to convert said actual current to a first voltage (V3) proportional to said actual current;
    • c. means (32) to generate a second voltage from said first voltage (V3), said second voltage proportional to an approximate value equal to the rms current of said load (2);
    • d. means (44) for integrating said second voltage to provide a trip signal (V10) representative of a predetermined full load carrying capacity of said AC load (2);
    • e. means (46) for comparing said trip signal (V10) with a predetermined trip reference voltage level (12), said comparator means (46) producing a drive output signal when said trip signal (V10) is a lessor magnitude that said trip reference voltage level (12), and said comparator means (46) producing a turn-off drive output signal when said trip signal (V10) is a greater magnitude than said trip reference voltage level (12) indicative of an overload condition; and
    • f. means (22) for removing said AC source from said load responsive to said drive output signal when said overload condition exists;
       characterised in that said second voltage generating means (32) includes an approximation circuit, said approximation circuit having first means (40) to generate a voltage (V5) from said first voltage (V3) proportionally equivalent to an average value of said actual current, second means (38) to generate a voltage from said first voltage (V3) proportionally equivalent to a peak value of said actual current, and third means (42) to sum a fraction of said voltage from said first means (40) with a fraction of said voltage from said second means (38) to provide said second voltage (V6) proportional to the rms current of said load.
  2. A solid state overload protective apparatus as claimed in claim 1 characterised in that said approximation circuit solves an approximation equation to provide said output signal proportional to the rms current of said load (2).
  3. A solid state overload protective apparatus as claimed in claim 1 or 2 characterised in that said approximation equation to provide said output signal proportional to the rms current of said load (2) is equivalent to the equation Irms = (0.22*Ipk) + (0.766*Iave)    where: Irms is the rms current of said load (2), Ipk is the peak current of said load (2), and Iave is the average current of said load (2).
  4. A solid state overload protective apparatus as claimed in any preceding claim characterised in that said AC source is a single phase source.
  5. A solid state overload protective apparatus as claimed in any one of claims 1 to 3 characterised in that said AC source is a polyphase source.
Anspruch[fr]
  1. Appareil de protection contre les surcharges à semiconducteurs, pour une charge alternative (2) alimentée à partir d'une source alternative (L1 à L3), comprenant :
    • a) des moyens (4) pour détecter le courant réel fourni à ladite charge (2) à partir de ladite source alternative (L1 à L3) ;
    • b) des moyens (36) pour convertir ledit courant réel en une première tension (V3) proportionnelle audit courant réel ;
    • c) des moyens (32) pour générer une deuxième tension à partir de ladite première tension (V3), ladite deuxième tension étant proportionnelle à une valeur approximative égale au courant efficace de ladite charge (2) ;
    • d) des moyens (44) pour intégrer ladite deuxième tension afin de fournir un signal de déclenchement (V10) représentatif d'une capacité à supporter une pleine charge prédéterminée de ladite charge alternative (2) ;
    • e) des moyens (46) pour comparer ledit signal de déclenchement (V10) à un niveau de tension de référence de déclenchement prédéterminé (12), lesdits moyens comparateurs (46) produisant un signal de sortie d'actionnement, lorsque ledit signal de déclenchement (V10) est d'une amplitude inférieure audit niveau de tension de référence de déclenchement (12), et lesdits moyens comparateurs (46) produisant un signal de sortie d'arrêt d'actionnement, lorsque ledit signal de déclenchement (V10) est d'une amplitude supérieure audit niveau de tension de référence de déclenchement (12), indicatif d'une condition de surcharge ; et
    • f) des moyens (22) pour couper l'alimentation par ladite source alternative de ladite charge, réagissant audit signal de sortie d'actionnement lorsque se produit ladite condition de surcharge ;
    caractérisé en ce que lesdits moyens de génération d'une deuxième tension (32) incluent un circuit d'approximation, ledit circuit d'approximation ayant des premiers moyens (40) pour générer une tension (V5), à partir de ladite première tension (V3), proportionnellement équivalente à une valeur moyenne dudit courant réel, des deuxièmes moyens (38) pour générer une tension, à partir de ladite première tension (V3), proportionnellement équivalente à une valeur de crête dudit courant réel, et des troisièmes moyens (42) pour additionner une fraction de ladite tension provenant desdits premiers moyens (40) avec une fraction de ladite tension provenant desdits deuxièmes moyens (38) afin de fournir ladite deuxième tension (V6) proportionnelle au courant efficace de ladite charge.
  2. Appareil de protection contre les surcharges à semiconducteurs selon la revendication 1, caractérisé en ce que ledit circuit d'approximation résout une équation d'approximation pour fournir ledit signal de sortie proportionnel au courant efficace de ladite charge (2).
  3. Appareil de protection contre les surcharges à semiconducteurs selon la revendication 1 ou 2, caractérisé en ce que ladite équation d'approximation, pour fournir ledit signal de sortie proportionnel au courant efficace de ladite charge (2), est équivalente à l'équation : Irms = (0,22 * Ipk) + (0,766 * Iave) dans laquelle Irms est le courant efficace de ladite charge (2), Ipk est le courant de crête de ladite charge (2) et Iave est le courant moyen de ladite charge (2).
  4. Appareil de protection contre les surcharges à semiconducteurs selon une quelconque des revendications précédentes, caractérisé en ce que ladite source alternative est une source monophasée.
  5. Appareil de protection contre les surcharges à semiconducteurs selon une quelconque des revendications 1 à 3, caractérisé en ce que ladite source alternative est une source polyphasée.






IPC
A Täglicher Lebensbedarf
B Arbeitsverfahren; Transportieren
C Chemie; Hüttenwesen
D Textilien; Papier
E Bauwesen; Erdbohren; Bergbau
F Maschinenbau; Beleuchtung; Heizung; Waffen; Sprengen
G Physik
H Elektrotechnik

Anmelder
Datum

Patentrecherche

Patent Zeichnungen (PDF)

Copyright © 2008 Patent-De Alle Rechte vorbehalten. eMail: info@patent-de.com