PatentDe  


Dokumentenidentifikation EP0571179 01.12.2005
EP-Veröffentlichungsnummer 0000571179
Titel Verfahren und Gerät zur Verbindungsprüfung eines elektronischen Geräts
Anmelder Sony Corp., Tokio/Tokyo, JP
Erfinder Okumoto, Koji, Tokyo 141, JP;
Matsuno, Katsumi, Tokyo 141, JP;
Shiono, Toru, Tokyo 141, JP;
Senuma, Toshitaka, Tokyo 141, JP;
Fukuda, Tokuya, Tokyo 141, JP;
Takada, Shinji, Tokyo 141, JP
Vertreter Mitscherlich & Partner, Patent- und Rechtsanwälte, 80331 München
DE-Aktenzeichen 69333890
Vertragsstaaten DE, FR, GB
Sprache des Dokument EN
EP-Anmeldetag 18.05.1993
EP-Aktenzeichen 933038366
EP-Offenlegungsdatum 24.11.1993
EP date of grant 26.10.2005
Veröffentlichungstag im Patentblatt 01.12.2005
IPC-Hauptklasse G01R 31/318
IPC-Nebenklasse G06F 11/26   

Beschreibung[en]

This invention relates to a method of testing connections of input and output terminals of integrated circuits constituting an electronic apparatus.

Conventional integrated circuits typically have, as shown in Figure 12 of the accompanying drawings, a plurality of parallel input terminals PI and parallel output terminals PO for data as well as a serial interface SIF by way of which serial communication is performed with a microcomputer or another integrated circuit (IC). The serial interface SIF includes a serial input terminal SI for data, a serial output terminal SO for data, a clock terminal SCK for communication, and a chip select terminal CS for selection of the integrated circuit. In actual integrated circuits, however, the parallel input terminals PI and the parallel output terminals PO are not always arranged regularly in this manner, and some integrated circuits have terminals which are used for both of inputting and outputting operations. Some other integrated circuits have no parallel input terminals. In Figure 12, the integrated circuit is shown constructed in such a manner as described above only for simplification of description.

When a plurality of such integrated circuits are connected to each other, as shown in Figure 13 of the accompanying drawings, the parallel output terminals PO of a first integrated circuit ICA are connected to the parallel input terminals PI of a second integrated circuit ICB, and the serial input terminals SI, the serial output terminals SO and the clock terminals SCK of the serial interfaces SIF of the integrated circuits ICA and ICB are connected commonly, respectively. Meanwhile, the chip select terminals CS of the integrated circuits ICA and ICB are connected separately from each other to a controlling microcomputer COM so that the microcomputer COM may select the other party of communication by way of the chip select terminals CS to perform time-division communication.

By the way, when a plurality of integrated circuits of the type described above are connected to each other so as to communicate data with each other, it should be tested whether or not the parallel input terminals PI and the parallel output terminals PO of the integrated circuits are individually connected with certainty. Particularly where a large number of integrated circuits are arranged in a high density on a circuit board of a limited area, wiring processing is complicated, resulting in a problem that it is further difficult to test a connection condition of the wiring lines with certainty.

One of solutions to this problem is a testing method called boundary scan, which is disclosed, for example, in IEEE Std 1149.1-1990, May 21, 1990. Referring to Figure 14 of the accompanying drawings, an integrated circuit IC11, which is constructed so as to allow the boundary scan, has, in addition to parallel input terminals PI and parallel output terminals PO for data and a serial interface SIF for serial communication, a test interface TIF for boundary scan.

The test interface TIF includes a test serial input terminal TSI for serially inputting data from the outside, a test serial output terminal TSO for outputting inputted test data serially, a test clock input terminal TCK for inputting a clock signal for processing of test data, and a test mode select terminal TMS for inputting an instruction to set the integrated circuit IC11 to a test mode.

Referring now to Figure 15 of the accompanying drawings, the integrated circuit IC11 has, in the inside thereof, boundary scan (S/C) cells BC1 to BC4 corresponding to the input terminals PI1 to PI4 of the parallel input terminals PI between the parallel input terminals PI and a function logic circuit FLG for executing predetermined data processing. Further, boundary scan (S/C) cells BC5 to BC8 are provided corresponding to the output terminals PO5 to PO8 of the parallel output terminals PO between the parallel output terminals PO and the function logic circuit FLG. It is to be noted that the test clock input terminal TCK and the test mode select terminal TMS are omitted in Figure 15.

Figure 16(a) of the accompanying drawings shows an exemplary detailed construction of the boundary scan cells BC1 to BC4 of Figure 15 while Figure 16(b) of the accompanying drawings shows an exemplary detailed construction of the boundary scan cells BC5 to BC8.

Referring first to Figure 16(a), data inputted by way of an input terminal PIi (in the arrangement shown in Figure 15, i is an integer from 1 to 4) is sent out to the function logic circuit FLG and a first input of a multiplexer MUX. Output data from a boundary scan cell at a preceding stage (that is, input data to the test serial input terminal TSI when the boundary scan cell shown is the boundary scan cell BC1, but when the boundary scan cell shown is any of the other boundary scan cells BC2 to BC4, output data from a preceding one of the boundary scan cells BC1 to BC3, respectively) is inputted to a second input of the multiplexer MUX. When the multiplexer MUX is set to a test mode, it fetches data from the input terminal PIi and outputs it to a D-type flip-flop D-FF, but when a signal "SHIFT DR" is inputted to the multiplexer MUX, the multiplexer MUX outputs data received from the boundary scan cell at the preceding stage to the D-type flip-flop D-FF. Then, when a clock signal CLOCK DR is sent out to the D-type flip-flop in this condition, the output of the D-type flip-flop D-FF is transferred to the boundary scan cell at the next stage.

Referring now to Figure 16(b), data inputted from the function logic circuit FLG is inputted to a first input of a multiplexer MUX. Meanwhile, data inputted from a boundary scan cell at a preceding stage is inputted to a second input of the multiplexer MUX by way of a D-type flip-flop D-FF. When the multiplexer MUX is set to a test mode, the output of the D-type flip-flop D-FF is sent out to an output terminal POj (in the arrangement of Figure 15, j is an integer from 5 to 8), but in an ordinary operation mode, data inputted from the function logic circuit FLG is sent out to the output terminal POj. The output of the D-type flip-flop D-FF is outputted also to a next stage (that is, to the test serial output terminal TSO when the boundary scan cell shown is the boundary scan cell BC8, but when the boundary scan cell shown is any of the other boundary scan cells BC5 to BC7, to a following one of the boundary scan cells BC6 to BC8, respectively).

It is to be noted that, though not shown, the integrated circuit IC11 of Figure 15 includes circuits for generating and sending out a signal "SHIFT DR" and a clock signal CLOCK DR to the boundary scan cells and an ordinary signal processing circuit for processing, in an ordinary operation mode, data inputted by way of the serial interface SIF to perform setting of a mode of the function logic circuit FLG, setting of a parameter and so forth.

In a test mode, the integrated circuit IC11 constructed in such a manner as described above operates in the following manner.

  • 1. Serial data of 4 bits inputted by way of the test serial input terminal TSI is stored once into the boundary scan cells BC1 to BC4 and then transferred to the boundary scan cells BC5 to BC8, respectively, in response to a clock signal CLOCK DR, whereafter it is outputted by way of the test serial output terminal TSO.
  • 2. Data of 4 bits inputted parallelly by way of the input terminals PI1 to PI4 is stored once into the boundary scan cells BC1 to BC4 and then transferred to the boundary scan cells BC5 to BC8, respectively, in response to a clock signal CLOCK DR, whereafter it is outputted as serial data by way of the test serial output terminal TSO.
  • 3. Serial data of 4 bits inputted by way of the test serial input terminal TSI is stored once into the boundary scan cells BC1 to BC4 and then transferred to the boundary scan cells BC5 to BC8, respectively, in response to a clock signal CLOCK DR, whereafter it is outputted as parallel data by way of the corresponding output terminals PO5 to PO8, respectively.

The integrated circuit IC11 having the test interface TIF and the boundary scan cells BC1 to BC8 in this manner and integrated circuits IC12 to IC14 having a similar construction are connected to each other in such a manner as shown in Figure 17 of the accompanying drawings, and test data TD in the form of serial data of 4 bits for testing is inputted to the test serial input terminal TSI of the first integrated circuit IC11. The test data TD is stored into the boundary scan cells BC5 to BC8 provided on the parallel output terminals PO side of the integrated circuit IC11 shown in Figure 15, and then outputted from the parallel output terminals PO to the input terminals PI of the second integrated circuit IC12 connected to the corresponding parallel output terminals PO of the first integrated circuit IC11.

The test data TD inputted to the parallel input terminals PI of the second integrated circuit IC12 is stored into the boundary scan cells (similar to the boundary scan cells BC1 to BC4 of Figure 15) provided corresponding to the parallel input terminals PI of the second integrated circuit IC12, and then transferred to the boundary scan cells (corresponding to the boundary scan cells BC5 to BC8 of Figure 15) corresponding to the parallel output terminals PO of the integrated circuit IC12, whereafter it is outputted from the test serial output terminal TSO. Thereafter, the test data TD is inputted to and outputted from each of the integrated circuits IC13 and IC14 similarly by way of the test serial input terminal TSI and the test serial output terminal TSO.

As the test data TD is outputted by way of parallel signal lines between the parallel output terminals PO of the integrated circuit IC11 and the parallel input terminals PI of the integrated circuit IC12, when, for example, "1111" is inputted as the test data TD, if the parallel signal lines between the parallel output terminals PO of the integrated circuit IC11 and the parallel input terminals PI of the integrated circuit IC12 have some disconnection or some incomplete connection, then the serial data outputted from the test serial output terminal TSO of the second integrated circuit IC12 presents "0" only at the bit or bits thereof corresponding to the failed signal line or lines and is outputted, for example, as data of "1011".

Accordingly, the connection condition between the first and second integrated circuits IC11 and IC12 can be tested based on the output data.

It is to be noted that, while, in actual integrated circuits, for example, also the integrated circuits IC11 and IC13 may be connected to each other or the output of the integrated circuit IC12 may be inputted to the integrated circuit IC11, the circuit system wherein the integrated circuits are connected regularly to each other is shown in Figure 17 for simplified illustration.

Figure 18 of the accompanying drawings shows a construction of a previously proposed an electronic apparatus testing system. In Figure 18, like elements to those of Figures 14 and 15 are denoted by like reference characters.

Referring to Figure 18, an electronic apparatus 20 such as a video tape recorder integrated with a camera includes a pair of integrated circuits IC21 and IC22 on a common circuit board. The parallel output terminals PO of the integrated circuit IC21 are connected to the parallel input terminals PI of the integrated circuit IC22 so that data may be communicated between the integrated circuits IC21 and IC22. The serial interfaces SIF of the integrated circuits IC21 and IC22 are individually connected to a microcomputer COM by way of a selector 23 and an internal communication bus 24 so as to perform serial communication between the microcomputer COM and the integrated circuits IC21 and IC22.

In the electronic apparatus 20 of the construction described above, an external terminal section 25 is connected to the selector 23, and when a select terminal SEL of the external terminal section 25 is controlled to a high ("H") level, the selector 23 is changed over from the microcomputer COM to the external terminal section 25 as indicated by broken lines in Figure 18.

A testing apparatus 27 is connected to the external terminal section 25 by way of a first bidirectional communication bus 26 such that the testing apparatus 27 transmits various control data to the external terminal section 25 and communicates test data from and to the internal communication bus 24 of the electronic apparatus 20 by way of the external terminal section 25.

An external bus interface 28 is connected to the microcomputer COM, and the testing apparatus 27 is connected to the external bus interface 28 by way of an external communication bus 29 serving as a second bidirectional communication bus. The external communication bus 29 is used for communication of data which are used to effect remote control of the electronic apparatus 20, setting of a mode of the integrated circuits IC21 and IC22, setting of a parameter and so forth, and is particularly used here in order to allow the testing apparatus 27 to transmit to the microcomputer COM a notification to conduct a test. The external bus interface 28 and the external communicatibn bus 29 may be, for example, those called LANC (Local Application Control Bus System) proposed by the applicant of the present application. A description of the LANC system is given in United States Patent Application No. 4,713,702 assigned to the same assignee.

When the select terminal SEL of the external terminal section 25 is controlled to the "H" level by the testing apparatus 27, the selector 23 is changed over from the microcomputer COM to the external terminal section 25. In this condition, the test serial output terminal TSO, the test serial input terminal TSI and the test clock terminal TCK of the external terminal section 25 are connected to the serial input terminals SI, the serial output terminals SO and the clock input terminals SCK, respectively, of the serial interfaces SIF of the integrated circuits IC21 and IC22.

Further, in this instance, a chip select terminal CSA of the external terminal section 25 is connected to the chip select terminal CS of the integrated circuit IC21, and another chip select terminal CSB of the external terminal section 25 is connected to the chip select terminal CS of the integrated circuit IC22. The integrated circuits IC21 and IC22 are thus caused to operate independently of each other using the two chip select terminals CSA and CSB so that data may not be outputted at the same time from the serial output terminals SO of the integrated circuits IC21 and IC22 to the external communication bus 24 connected to the serial interfaces SIF.

Here, the test mode select terminal TMS of the external terminal section 25 is connected to the test mode select terminals TMS of the integrated circuits IC21 and IC22 so that the integrated circuits IC21 and IC22 may be set to a test mode in response to the logic level at the test mode select terminal TMS.

In order to conduct a test, first the chip select terminal CSA of the external terminal section 25 is changed to the "H" level to select the integrated circuit IC21, and the test mode select terminal TMS of the external terminal section 25 is changed to the "H" level to put the integrated circuit IC21 into a test mode. Then, test data is inputted to the serial input terminal SI of the integrated circuit IC21 while a clock signal is inputted to the clock input terminal SCK of the integrated circuit IC21. The test data thus inputted is transferred from the boundary scan cells BC1 to BC4 (not shown in Figure 18) to the boundary scan cells BC5 to BC8 (not shown in Figure 18) in synchronism with the clock signal inputted to the clock input terminal SCK of the integrated circuit IC21. In this condition, the chip select terminal CSA of the external terminal section 25 is changed to a low ("L") level to put the integrated circuit IC21 into a hold mode so as to hold the data in the boundary scan cells BC5 to BC8.

Subsequently, the chip select terminal CSB of the external terminal section 25 is changed to the "H" level to select the integrated circuit IC22, and the test mode select terminal TMS of the external terminal section 25 is changed to the "H" level to set the integrated circuit IC22 to a test mode. Then, the integrated circuit IC 22 fetches the data held in the boundary scan cells BC5 to BC8 of the integrated circuit IC21 into the parallel input terminal PI. Subsequently, the test data fetched into the parallel input terminals PI of the integrated circuit IC22 are transferred from the boundary scan cells BC1 to BC4 to the boundary scan cells BC5 to BC8, respectively, of the integrated circuit IC22 and then outputted from the serial output terminal SO of the integrated circuit IC22 in synchronism with a clock signal inputted to the clock input terminal SCK of the integrated circuit IC22.

In the testing system described above, the integrated circuits IC21 and IC22 have no test interface TIF, but each inputs test data at the serial interface SIF thereof. Therefore, each of the integrated circuits IC21 and IC22 requires a switching circuit for sending out, in an ordinary operation mode, data inputted by way of the serial interface SIF to an ordinary signal processing circuit, but sending out, in a test mode, data inputted by way of the serial interface SIF to the boundary scan cells. Meanwhile, since the test interface TIF is eliminated, the integrated circuit is simplified in construction.

However, the electronic apparatus testing system of Figure 18 requires, in addition to the communication lines for communicating test data between the testing apparatus and the integrated circuits, an additional control signal line for putting the integrated circuits into a test mode. Consequently, where a plurality of integrated circuits are provided in an electronic apparatus, a number of control signal lines equal to the number of integrated circuits are wired on a circuit board, and the circuit board is required to have an additional occupation area for the control lines. Also the external terminal section requires the test mode select terminal TMS for connection to the control signal lines.

Further, since an operation of fetching test data by way of the parallel input terminals of an integrated circuit and another operation of transferring the thus fetched test data are separate from each other, a circuit for realizing such separate operations is required, resulting in complicated construction and increase in size of the integrated circuit.

GB-A-2,221,072 discloses an integrated circuit which may be switched to a test mode upon recognition of receipt of a predetermined sequence of codes.

GB-A-2,195,185 discloses an arrangement for testing an integrated circuit in which series connected boundary scan chains may be selectively by-passed upon receipt of an appropriate control signal.

EP-A-0,461,714 discloses a self test mechanism in a data processing system using a shift register to input and then apply a control pattern and subsequently using the shift register to capture and output the system response.

Various aspects of the invention are set out in the accompanying claims.

With the testing method and apparatus of the present invention, the following advantages can be anticipated in at least preferred embodiments:

  • 1. Since a control signal line for setting an integrated circuit to a test mode is unnecessary, the area of a circuit board for the integrated circuits is reduced;
  • 2. When binary scan data is to be inputted by way of an external terminal section, a test mode select terminal of the external terminal section can be eliminated;
  • 3. Since fetching of test data and transfer of the thus fetched test data are performed in a simultaneous operation, a reduction in size of the circuit for realizing the operations can be realized;
  • 4. Since a switching apparatus for exclusive use for switching between an external terminal section and a communication bus is unnecessary, simplification of the testing apparatus and reduction in number of parts of an electronic apparatus can be achieved;
  • 5. Since, when an electronic apparatus is viewed from the testing apparatus, communication of data is performed to and from a data area (RAM) on an imaginary space of a microcomputer, there is no necessity to be aware of the internal structure of the electronic apparatus;
  • 6. The testing apparatus is only required to support the protocol on the external communication bus; and
  • 7. Since a test of test data is performed with the testing apparatus, even when the integrated circuits are modified, it is possible to cope with this only by changing commands and/or boundary scan data to be transmitted from the testing apparatus. Accordingly, the necessity of a change of a program of a microcomputer of an electronic apparatus is eliminated.

An embodiment of the invention will now be described, by way of example only, with reference to the accompanying drawings in which:

  • Figure 1 is a block diagram showing one embodiment of electronic apparatus testing system to which the present invention is applied;
  • Figure 2 is a diagrammatic view illustrating a format of data to be transmitted from a testing apparatus to a microcomputer of the electronic apparatus testing system of Figure 1;
  • Figure 3 is a diagrammatic view illustrating a format of data to be transmitted from the microcomputer of the electronic apparatus testing system of Figure 1 to an integrated circuit;
  • Figure 4 is a diagrammatic view showing a construction of a RAM of the microcomputer of Figure 1;
  • Figure 5 is a block diagram showing a construction of an integrated circuit to be boundary scan tested by the electronic apparatus testing system of Figure 1;
  • Figure 6 is a flow chart illustrating operation of a boundary scan control circuit of the electronic apparatus testing system of Figure 1;
  • Figure 7 is a time chart illustrating operation of the integrated circuit for boundary scan;
  • Figure 8 is a time chart illustrating operation of the boundary scan control circuit;
  • Figure 9 is a flow diagram illustrating a testing procedure of the electronic apparatus testing system of Figure 1;
  • Figures 10(a) to 10(c) and 11(a) to 11(c) are diagrammatic views showing conditions of integrated circuits at different steps of the operation illustrated in Figure 9;
  • Figure 12 is a diagrammatic view showing a construction of a conventional integrated circuit;
  • Figure 13 is a wiring diagram illustrating a connection condition between a plurality of integrated circuits and a microcomputer;
  • Figure 14 is a diagrammatic view showing a construction of a conventional integrated circuit for boundary scan;
  • Figure 15 is a block diagram showing an internal construction of the integrated circuit for boundary scan shown in Figure 14;
  • Figures 16(a) and 16(b) are block diagrams showing constructions of conventional boundary scan cells;
  • Figure 17 is a diagrammatic view showing a plurality of integrated circuits for which boundary scanning is performed; and
  • Figure 18 is a block diagram showing a construction of an electronic apparatus testing system proposed by the same assignee.

Referring first to Figure 1, there is shown an example of an electronic apparatus testing system to which the present invention is applied. An electronic apparatus 1 such as, for example, a video tape recorder integrated with a camera includes a plurality of integrated circuits (ICs) provided on a single circuit board. In Figure 1, only three of the integrated circuits, that is, integrated circuits IC1 to IC3, are shown. Parallel output terminals PO of the integrated circuit (IC) IC1 are connected to parallel input terminals PI of the integrated circuit IC2, while parallel output terminals of the integrated circuit IC2 are connected to parallel input terminals PI of the integrated circuit IC3, so that data may be communicated between the integrated circuits IC1 and IC2 and between the integrated circuits IC2 and IC3.

Serial interfaces SIF of the integrated circuits IC1 to IC3 are connected to a microcomputer 6 by way of an internal communication bus 2 so that serial communication may be performed between the microcomputer 6 and the integrated circuits IC1 to IC3.

The microcomputer 6 in the electronic apparatus 1 constructed in such a manner as described above is connected to a testing apparatus 5 by way of an external bus interface 3 and an external communication bus 4. The external bus interface 3 and the external communication bus 4 may be, for example, the LANC described hereinabove with reference to Figure 18 and is used for remote controller control of the electronic apparatus 1, setting of a mode of the integrated circuits IC1 to IC3, setting of a parameter and so forth. Here, the testing apparatus 5 performs communication of test data, transmission of commands and so forth to and from the microcomputer 6.

Referring now to Figure 2, there is shown a construction of data to be transmitted from the testing apparatus 5 to the microcomputer 6 in the electronic apparatus testing system shown in Figure 1. The data includes an IC designating command for designating an integrated circuit into which boundary scan (B/S) data is to be written, a data length of the boundary scan data to be written into boundary scan (B/S) cells of the integrated circuit, test data to be transmitted from the microcomputer 6 to the integrated circuit and a boundary scan (B/S) mode setting command. The boundary scan mode setting command is a command to send boundary scan data to a designated integrated circuit. Accordingly, actually another command to set the microcomputer 6 itself to a boundary scan mode is necessitated separately.

Figure 3 illustrates a construction of data to be transmitted from the microcomputer 6 in the electronic apparatus testing system of Figure 1 to a serial input terminal SI of an integrated circuit. Referring to Figure 3, the data includes a category code Ci produced from the boundary scan data by the microcomputer 6 for setting an integrated circuit to a test mode or an ordinary operation mode, and boundary scan data or ordinary data to be inputted to an integrated circuit to which setting of a mode has been performed. The category code Ci may be constituted from one bit of "0" or "1" in principle, but preferably is constituted from several bits. Particularly, when each integrated circuit has a plurality of functions to be used switchably, the category code Ci is constituted from a plurality of bits.

Referring now to Figure 4, there is shown a construction of a RAM of the microcomputer 6 in the electronic apparatus testing system of Figure 1. The RAM has a command area CA for storing therein a boundary scan mode setting command, a boundary scan data length and an integrated circuit designating command as illustrated in Figure 2, an output data area DA1 for storing therein boundary scan data inputted from the testing apparatus and to be outputted to an integrated circuit, and an input data area DA2 for storing therein boundary scan data inputted from an integrated circuit.

Referring now to Figure 5, there is shown a construction of an integrated circuit for boundary scan, which is tested by the electronic apparatus testing system of Figure 1. The integrated circuit for boundary scan shown is a modification to or an improvement in the conventional integrated circuit for boundary scan described hereinabove with reference to Figure 15. In particular, the integrated circuit for boundary scan is constructed such that a boundary scan control circuit 8 discriminates the category code Ci at the beginning of the data inputted by way of a serial input terminal SI and controls a pair of switching circuits SW1 and SW2 in accordance with a result of the discrimination. If the category code Ci indicates a test mode, then the boundary scan control circuit 8 selects terminals b of the switching circuits SW1 and SW2 so that inputted data are transferred to boundary scan cells BC1 to BC8, but on the other hand, if the category code Ci indicates an ordinary operation mode, then the boundary scan control circuit 8 selects the other terminals a of the switching circuits SW1 and SW2 so that inputted data are transferred to an ordinary signal processing circuit not shown of the integrated circuit for boundary scan. Here, the switching circuits SW1 and SW2 may have a similar construction to that of the multiplexer MUX shown in Figure 16. Meanwhile, the ordinary signal processing circuit may be constituted from a plurality of registers and executes setting of a mode of the integrated circuit IC1 to IC3 and processing of data in an ordinary operation mode such as setting of a parameter. It is to be noted that control signals inputted from the boundary scan control circuit 8 to the boundary scan cells BC1 to BC8 are represented by broken lines in Figure 5 are clock signals SCK.

Operation of the integrated circuit for boundary scan shown in Figure 5 is illustrated in Figures 6 to 8. Referring first to Figure 5 and also to Figure 6 which illustrates operation of the boundary scan control circuit 8 of the integrated circuit for boundary scan, the boundary scan control circuit 8 first discriminates the level of an input signal to the chip select terminal CS, and if the input signal level is the "L" level (= active), then the boundary scan control circuit 8 fetches the category code Ci of the first n bits inputted to the serial input terminal SI in response to a rising edge of the clock signal SCK (steps S1 and S2). Then, if the n bits thus fetched indicate a test mode, then the boundary scan control circuit 8 selects the terminals b of the switching circuits SW1 and SW2 so that boundary scan is performed with following bit data beginning with the n+1th bit of the data inputted to the serial input terminal SI. On the other hand, if the n bits fetched indicate an ordinary operation mode, the boundary scan control circuit 8 selects the other terminals a of the switching circuits SW1 and SW2 so that ordinary signal processing is executed (steps S3, S4 and S5).

Referring now to Figure 5 and Figures 7 and 8 which illustrate a boundary scanning operation of the integrated circuit for boundary scan shown in Figure 5, the boundary scan control circuit 8 first discriminates the level of an input signal to the chip select terminal CS, and if the input signal level is the "L" level (= active), then the boundary scan control circuit 8 fetches test data inputted to the parallel input terminals PI into the boundary scan cells BC1 to BC4 in response to a falling edge of a first clock of the clock signal SCK (steps S11 to S13 in Figure 8; the waveform "CAPTURE" in Figure 7). Then, the boundary scan control circuit 8 discriminates the level of the input signal to the chip select terminal CS, and if the input signal level is the "L" (= active), then the boundary scan control circuit 8 outputs the test data, which have been inputted by way of the serial input terminal SI and fetched into the boundary scan cells BC1 to BC4 and is constituted from bit data of bits beginning with the n+1th bit, from the serial output terminal SO by way of the boundary scan cells BC5 to BC8 in response to rising edges of clocks of the clock signal SCK after the first clock (steps S14 to S16).

It is to be noted that, when the category code Ci indicates an ordinary operation mode, the signal CAPTURE illustrated in Figure 7 is not used, but data for an ordinary operation mode inputted from the serial input terminal SI is sent out from the switching circuit SW1 to the ordinary signal processing circuit and then outputted from the serial output terminal SO by way of the switching circuit SW2.

Subsequently, a procedure when the connection condition between the parallel output terminals PO of the integrated circuit IC1 and the parallel input terminals PI of the integrated circuit IC2 and the connection condition between the parallel output terminals PO of the integrated circuit IC2 and the parallel input terminals PI of the integrated circuit IC3 are successively tested will be described with reference to Figures 1 to 11.

First, the testing apparatus 5 sets the microcomputer 6 to a boundary scan mode by way of the external communication bus 4 and the external bus interface 3. In the boundary scan mode, the microcomputer 6 stops its ordinary operation and enters a boundary scan mode setting command waiting condition.

Subsequently, the testing apparatus 5 sends out such data as illustrated in Figure 2 to the microcomputer 6. Upon reception of the data, the microcomputer 6 stores the integrated circuit designating command, the boundary scan data length and the boundary scan mode setting command included in the received data into the command area CA of the RAM thereof and stores the transmission data of the received data into the data area DA1 (step S1 in Figure 9). Here, the transmission data includes the category code C1 for setting the integrated circuit IC1 to a test mode and data P1 = "11110000" for setting the parallel output terminals PO of the integrated circuit IC1 to test data "1111"; the IC designating command is a command designating the integrated circuit IC1; and the boundary scan mode setting command is a command to transmit the boundary scan data stored in the output data area DA1 of the RAM to an integrated circuit and store data read out from the integrated circuit into the input data area DA2 of the RAM. In this instance, data, which have been stored in an ordinary operation mode, still remain in the integrated circuits IC1 to IC3 (refer to the mark * in Figure 10(a)).

Subsequently, the microcomputer 6 reads the IC designating command stored in the command area CA of the RAM and controls the chip select terminal CSA thereof to the "L" level to select the integrated circuit IC1, whereafter it reads out the category code C1 and the data P1 from the output data area DA1 of the RAM and transmits them to the serial input terminal SI of the integrated circuit IC1. The boundary scan control circuit 8 in the integrated circuit IC1 discriminates that the category code C1 represents a test mode, and changes over the switching circuits SW1 and SW2 to the terminals b side so that the data Pi = "11110000" is transferred to the boundary scan cells BC1 to BC8 in synchronism with a clock signal inputted to the clock terminal SCK. Thereupon, the data "********", which has been stored into the integrated circuit IC1 before the test mode is entered, is read out by way of the serial output terminal SO of the integrated circuit IC1 and stored into the input data area DA2 of the integrated circuit IC1 (step S2). The data may be abandoned since it is not used for the test of the integrated circuit IC1. Since the test data "1111", which is the former half of the inputted data P1 is stored into the boundary scan cells BC5 to BC8 connected to the parallel output terminals PO of the integrated circuit IC1, the test data "1111" appears at the parallel output terminals PO. Since the data "0000" of the latter half is not used for the test, any other arbitrary bit pattern may be employed instead. After the transmission to the serial input terminal SI is completed, the microcomputer 6 controls the chip select terminal CSA thereof to the "H" level. Consequently, the integrated circuit IC1 is controlled to a hold mode. In the hold mode, the state of the integrated circuit IC1 does not change, and the data at the parallel output terminals PO of the integrated circuit IC1 maintains the test data "1111".

Subsequently, the testing apparatus 5 transmits the data illustrated in Figure 2 to the microcomputer 6. Upon reception of the data, the microcomputer 6 stores the data into the command area CA and the output data area DA1 of the RAM similarly as at step S1 (step S3 in Figure 9). Here, the boundary scan data of the received data includes the category code C2 for setting the integrated circuit IC2 to a test mode and data P2 = "11110000" for setting the parallel output terminals PO of the integrated circuit IC2 to the test data "1111"; and the IC designating command is a command designating the integrated circuit IC2. In this instance, the data P2 may be overwritten with the data P1, which has been stored into the output data area DA1 at step S1 in Figure 9, or otherwise be stored into another region of the output data area DA1. In the present embodiment, the data P2 is overwritten with the data P1 in order to save the RAM.

Subsequently, the microcomputer 6 reads the IC designating command and controls the chip select terminal CSB thereof to the "L" level to select the integrated circuit IC2, whereafter it reads out the category code C2 and the data P2 from the output data area DA1 of the RAM and transmits them to the serial input terminal SI of the integrated circuit IC2. The boundary scan control circuit 8 in the integrated circuit IC2 discriminates that the category code C2 represents a test mode, and changes over the switching circuits SW1 and SW2 to the terminals b side so that the test data "1111" at the parallel output terminals PO of the integrated circuit IC1 is caught at the parallel input terminals PO of the integrated circuit IC2 at a falling edge of a first clock (step S5 in Figure 9; Figure 10(c)). Thereafter, the data P2 is transferred to the boundary scan cells BC1 to BC8 at falling edges of clocks following the first clock. Thereupon, the data "****1111" (whose latter 4 bits "1111" have been caught from the test data "1111" from the parallel output terminals PO of the integrated circuit IC1) is read out by way of the serial output terminal SO of the integrated circuit IC2 and stored into the input data area DA2 of the microcomputer 6 (step S5 in Figure 9; Figure 11(a)). Thus, at the present step S5, reading out of the data P1 for testing the connection condition between the parallel output terminals PO of the integrated circuit IC1 and the parallel input terminals PI of the integrated circuit IC2 and writing of the data P2 for testing the connection condition between the parallel output terminals PO of the integrated circuit IC2 and the parallel input terminals PI of the integrated circuit IC3 are performed at a time. In this condition, the microcomputer 6 controls the chip select terminal CSB thereof to the "H" level to control the integrated circuit IC2 to a hold mode.

The latter 4 bits of the data "****1111" stored in the input data area DA2 of the microcomputer 6 is compared with the former 4 bits of the data P1 = "11110000', which has been stored into the output data area DA1 at step S1 in Figure 9, to test the connection condition between the parallel output terminals PO of the integrated circuit IC1 and the parallel input terminals PI of the integrated circuit IC2 (step S6 in Figure 9). While the comparison may be executed by either of the microcomputer 6 and the testing apparatus 5, if the electronic apparatus testing system is constructed such that the comparison is executed by the microcomputer 6, then when the configuration of integrated circuits is changed, the program for the microcomputer 6 must be changed, but otherwise if the electronic apparatus testing system is constructed such that the comparison is executed by the testing apparatus 5, then since stored contents of the input data area DA2 are read into the testing apparatus 5 by way of the external bus interface 3, it is possible to cope with such change of the configuration of the integrated circuits as mentioned above only by changing the program for the testing apparatus 5.

Subsequently, the testing apparatus 5 transmits the data illustrated in Figure 2 to the microcomputer 6. Upon reception of the data, the microcomputer 6 stores the data into the command area CA and the output data area DA1 of the RAM (step S7 in Figure 9). Here, the boundary scan data of the received data includes the category code C3 for putting the integrated circuit IC3 into a test mode and data P3 = "11110000" for setting the parallel output terminals PO of the integrated circuit IC3 to the test data "1111"; and the IC designating command is a command designating the integrated circuit IC3.

Subsequently, the microcomputer 6 reads the IC designating command and controls the chip select terminal CSC thereof to the "L" level to select the integrated circuit IC3, whereafter it reads out the category code C3 and the data P3 from the output data area DA1 of the RAM and transmits them to the serial input terminal SI of the integrated circuit IC3. The boundary scan control circuit 8 in the integrated circuit IC3 discriminates that the category code C3 represents a test mode, and changes over the switching circuits SW1 and SW2 to the terminals b side so that the test data "1111" at the parallel output terminals PO of the integrated circuit IC2 is caught at the parallel input terminals PO of the integrated circuit IC3 at a falling edge of a first clock (step S8 in Figure 9; Figure 11(b)). Thereafter, the data P3 is transferred to the boundary scan cells BC1 to BC8 at falling edges of clocks following the first clock. Thereupon, the data "****1111" is read out by way of the serial output terminal SO of the integrated circuit IC3 and stored into the input data area DA2 of the microcomputer 6 (step S9 in Figure 9; Figure 11(c)). Thus, at the present step S9, reading out of the test data P2 for testing the connection condition between the parallel output terminals PO of the integrated circuit IC2 and the parallel input terminals PI of the integrated circuit IC3 and writing of the data P3 for testing the connection condition between the parallel output terminals PO of the integrated circuit IC3 and the parallel input terminals PI of a following integrated circuit IC4 (not shown) are performed at a time.

The latter 4 bits of the data "****1111" stored in the input data area DA2 of the microcomputer 6 is compared with the former 4 bits of the data P2 = "11110000", which has been stored into the output data area DA1 at step S3 in Figure 9, to test the connection condition between the parallel output terminals PO of the integrated circuit IC2 and the parallel input terminals PI of the integrated circuit IC3 (step S10 in Figure 9).

Thereafter, a test is performed successively for the integrated circuits IC4, IC5, ... (not shown) in a similar manner. Then, after the test using the test data "1111" is completed, the test mode described above is repeated changing the test data to "0000". As a result, results of comparison between the test data "1111" and "0000" inputted to the integrated circuits IC1 to IC3 and so forth and data outputted from the serial output terminals SO of the integrated circuits IC1 to IC4 and so forth are obtained first, and if any of the results of comparison indicates a difference, there is a failure such as incomplete disconnection in the signal line corresponding to the data of the difference.

It is to be noted that the present invention is not limited to the embodiment described above and various alterations are possible in accordance with the scope of the present invention, and the present invention does not exclude such alterations from the scope of the present invention. For example, when an integrated circuit does not include an ordinary signal processing circuit and switching circuits SW1 and SW2 such as an oscillation circuit or a modulation circuit, the electronic apparatus testing apparatus may be constructed such that, without using a category code, test data is fetched by way of the parallel input terminals to execute boundary scanning at a point of time when it is discriminated that the input signal level at the chip select terminal CS has changed to the "L" level. Further, while, in the embodiment described above, the testing apparatus transmits data to the microcomputer by way of the external bus interface, alternatively data may be transmitted to the internal communication bus by way of the external terminal section similarly as in the previously proposed electronic apparatus testing system shown in Figure 18. Further, while, in the embodiment described above, the "L" level state at the chip select terminal CS and the clock terminal SCK is set active, alternatively the "H" level state may be set active.

In at least preferred embodiments the invention provides: a method of testing an electronic apparatus which eliminates a control signal line for setting an integrated circuit to a test mode and a test mode select terminal of an external terminal section; and a method of testing an electronic apparatus wherein fetching of test data and transfer of the thus fetched test data are performed in an integrated operation.

Having now fully described the invention, it will be apparent to one of ordinary skill in the art that many changes and modifications can be made thereto without departing from the scope of the invention as set forth herein.


Anspruch[de]
  1. Verfahren zum Testen eines Verbindungszustandes zwischen den Eingabe- und Ausgabe-Anschlüssen erster (IC1) und zweiter (IC2) benachbarter integrierter Schaltkreise, wobei jeder eine Vielzahl paralleler Daten-Eingabe/Ausgabe-Anschlüsse (PI/PO), serielle Eingabe- (SI) und serielle Ausgabe- (SO) Anschlüsse, einen Taktgeber-Anschluss (SCK), einen Chip-Auswahlanschluss (CS) und Boundary-Scan-Zellen (BC1-BC8) entsprechend der Vielzahl paralleler Daten-Eingabe/Ausgabe-Anschlüsse umfasst und wobei Daten zwischen den parallelen Ausgabe-Anschlüssen (PO) des ersten integrierten Schaltkreises und den parallelen Eingabe-Anschlüssen (PI) des zweiten integrierten Schaltkreises übertragen werden, wobei jeder der ersten und zweiten integrierten Schaltkreise (IC1, IC2) eine Diskriminierungs-Schaltung (8) für das Unterscheiden des Vorhandenseins oder des Fehlens eines Testmodusauswahl-Befehls für das Setzen von erstem und zweitem integrierten Schaltkreis (IC1, IC2) in einen Testmodus; wobei das Verfahren die Schritte umfasst:
    • Setzen in einen Modus, in der ein Verbindungszustand zwischen erstem und zweitem integrierten Schaltkreis mittels der Diskriminierungs-Schaltung (8) überprüft werden soll, durch das Übertragen eines Befehles von einer Testvorrichtung (5) zu einem Mikrocomputer (6) über eine externe Busschnittstelle (3);
    • Eingeben vorbestimmter Testdaten von dem seriellen Eingabe-Anschluss (SI) des ersten integrierten Schaltkreises (IC1), unter Steuerung durch den Mikrocomputer (6), wenn sich der erste integrierte Schaltkreis im Testmodus befindet, und Speichern der vorbestimmten Testdaten in den Boundary-Scan-Zellen (BC5-BC8) des ersten integrierten Schaltkreises (IC1);
    • Ausgeben der Testdaten von den parallelen Datenausgabe-Anschlüssen (PO) des ersten integrierten Schaltkreises (IC1) zu den parallelen Dateneingabe-Anschlüsse (PI) des zweiten integrierten Schaltkreises (IC2);
    • Auslesen der Testdaten aus den Boundary-Scan-Zellen (BC1-BC4), die den parallelen Daten-Eingabe/Ausgabe-Anschlüssen des zweiten integrierten Schaltkreises (IC2) entsprechend vorgesehen sind;
    • Senden der gespeicherten Daten über die externe Busschnittstelle (3) zur Testvorrichtung unter Steuerung durch den Mikrocomputer (6); und Vergleichen der Testdaten von den Boundary-Scan-Zellen (BCS-BC8), die den parallelen Ausgabe-Anschlüssen des ersten integrierten Schaltkreises mit den Testdaten der Boundary-Scan-Zellen (BC1-BC4) entsprechen, die den parallelen Eingabe-Anschlüssen des zweiten integrierten Schaltkreises entsprechen als eine Zustandsanzeige der Verbindung zwischen erstem und zweitem integrierten Schaltkreis.
  2. Verfahren nach Anspruch 1, wobei erster und zweiter integrierter Schaltkreis (IC1, IC2) jeweils Chip-Auswahl-Anschlüsse (CS) für das Freigeben von erstem und zweitem integrierten Schaltkreis umfassen und wobei das Verfahren ferner den Schritt des Bereitstellens eines Freigabesignals (ES) zu den jeweiligen Chip-Auswahl-Anschlüssen von erstem und zweitem integrierten Schaltkreise umfasst.
  3. Verfahren nach Anspruch 1, wobei die Diskriminierungs-Schaltungen (8) von erstem und zweitem integrierten Schaltkreis (IC1, IC2) betriebsbereit sind, um ersten und zweiten integrierten Schaltkreis in den Testmodus zu versetzen, wenn ein Testmodus-Auswahlbefehl an den jeweiligen seriellen Eingabe-Anschlüssen von erstem und zweitem integrierten Schaltkreis empfangen wird, und der Schritt zum Setzen von erstem und zweitem integrierten Schaltkreis in den Testmodus dadurch ausgeführt wird, dass der Testmodus-Auswahlbefehl dem seriellen Eingabe-Anschluss von erstem und zweitem integrierten Schaltkreis zugeführt wird.
  4. Verfahren nach Anspruch 3, wobei der erste integrierte Schaltkreis (IC1) von dessen Diskriminierungs-Schaltung gesteuert (8) wird, um die Testdaten, die seinem seriellen Eingabe-Anschluss zugeführt werden, in den Boundary-Scan-Zellen nur seriell zu speichern, lediglich wenn der Testmodus-Auswahlbefehl seinem seriellen Eingabe-Anschluss zugeführt wird.
  5. Verfahren nach Anspruch 1, das ferner den Schritt des Zuführens zweiter Testdaten zu dem seriellen Eingabe-Anschluss des zweiten integrierten Schaltkreises (IC2) umfasst und wobei der Schritt des Steuerns des zweiten integrierte Schaltkreises das Steuern des zweiten integrierte Schaltkreis umfasst, um die zweiten Testdaten in seinen Boundary-Scan-Zellen seriell zu speichern, wenn die parallelen Daten, die in seinen Boundary-Scan-Zellen gespeichert sind, als die Ausgabe-Testdaten von seinem seriellen Ausgabe-Anschluss seriell zugeführt werden.
  6. Verfahren nach Anspruch 5, wobei der Schritt des Steuerns des zweiten integrierten Schaltkreises (IC2) das Steuern des zweiten integrierten Schaltkreises umfasst, die zweiten Testdaten, die in seinen Boundary-Scan-Zellen gespeichert sind, als zweite parallele Daten von seinem parallelen Daten-Eingabe/Ausgabe-Anschluss, zuzuführen.
  7. Verfahren nach Anspruch 6, das ferner einen dritten integrierten Schaltkreis (IC3) umfasst, der einen parallelen Daten-Eingabe/Ausgabe-Anschluss (PI/PO), serielle Eingabe- (SI) und Ausgabe- (SO) Anschlüsse und Boundary-Scan-Zellen aufweist, die seinem parallelen Daten-Eingabe/Ausgabe-Anschluss zugeordnet sind, und der an seinem parallelen Daten-Eingabe/Ausgabe-Anschluss mit dem parallelem Daten-Eingabe/Ausgabe-Anschluss des zweiten integrierten Schaltkreises (IC2) verbunden ist, und wobei das Verfahren ferner die Schritte umfasst:
    • Steuern des dritten integrierten Schaltkreises (IC3), um in seinen Boundary-Scan-Zellen die zweiten parallelen Daten, die seinem parallelen Daten-Eingabe/Ausgabe-Anschluss von dem parallelem Daten-Eingabe/Ausgabe-Anschluss des zweiten integrierten Schaltkreises (IC2) zugeführt werden, zu speichern und die zweiten parallelen Daten, die in den Boundary-Scan-Zellen des dritten integrierte Schaltkreises gespeichert sind, als zweite Ausgabe-Testdaten von seinem seriellen Ausgabe-Anschluss seriell zuzuführen; und
    • Vergleichen der zweiten Ausgabe-Testdaten, die von dem seriellem Ausgabe-Anschluss des dritten integrierten Schaltkreises (IC3) zugeführt werden, mit den zweiten Testdaten, die dem seriellem Eingabe-Anschluss des zweiten integrierten Schaltkreises (IC2) zugeführt werden, als eine Zustandsanzeige der Verbindung zwischen zweitem und drittem integrierten Schaltkreis.
  8. Vorrichtung umfassend:
    • erste (IC1) und zweite (IC2) integrierte Schaltkreise, jeder umfassend eine Vielzahl paralleler Daten-Eingabe/Ausgabe-Anschlüsse (PI/PO), serielle Eingabe-(SI) und Ausgabe- (SO) Anschlüsse, einen Taktgeber-Anschluss (SCK), einen Chip-Auswahlanschluss (CS) und Boundary-Scan-Zellen (BC1-BC8) entsprechend der Vielzahl von parallelen Daten-Eingabe/Ausgabe-Anschlüssen, und eine Diskriminierungs-Schaltung (8) für das Unterscheiden des Vorhandenseins oder des Fehlens eines Testmodusauswahl-Befehls für das selektive Setzen von erstem und zweitem integrierten Schaltkreis (IC1, IC2) in einen Testmodus, und Vorrichtungen (5, 6, 8, SW1, SW2) für das Testen der Verbindungen von erstem und zweitem integrierten Schaltkreis; wobei die Vorrichtung für das Testen der Verbindungen so ausgebildet ist, dass Daten zwischen den parallelen Ausgabe-Anschlüssen (PO) des ersten integrierten Schaltkreises und den parallelen Eingabe-Anschlüssen (PI) des zweiten integrierten Schaltkreises übertragen werden; und
    • Diskriminierungs-Schaltungen (8) in jedem von erstem und zweitem integrierten Schaltkreis zum selektiven Setzen von erstem und zweitem integrierten Schaltkreis (IC1, IC2) in einen Testmodus, in dem ein Verbindungszustand zwischen erstem und zweitem integrierten Schaltkreis (IC1, IC2) überprüft werden soll;
    • eine in dem Testmodus betriebsbereite Testvorrichtung ausgebildet ist, um vorbestimmte Testdaten und den Testmodus-Auswahlbefehl zu generieren und die Daten dem seriellem Eingabe-Anschluss (SI) des ersten integrierten Schaltkreises (IC1) zuzuführen; wobei
    • der erste integrierte Schaltkreis (IC1) in dem Testmodus betriebsbereit ist, um die Testdaten in seinen Boundary-Scan-Zellen seriell zu speichern, und die Testdaten, die in seinen Boundary-Scan-Zellen gespeichert sind, als parallele Daten von dem ersten integrierten Schaltkreis an seinen parallelen Datenausgabe-Anschlüssen, zu dem zweiten integrierten Schaltkreis an seinen parallelen Dateneingabe-Anschlüssen zuzuführen; und
    • der zweite integrierte Schaltkreis in dem Testmodus betriebsbereit ist, um in seinen Boundary-Scan-Zellen die parallelen Daten zu speichern, die seinen parallelen Dateneingabe-Anschlüssen von den parallelen Datenausgabe-Anschlüssen des ersten integrierten Schaltkreises zugeführt werden; und
    • Mittel (5, 6) vorgesehen sind zum Vergleichen der Testdaten aus den Boundary-Scan-Zellen (BC5-BC8) entsprechend den parallelen Ausgabe-Anschlüssen des ersten integrierten Schaltkreises mit den Testdaten aus den Boundary-Scan-Zellen (BC1-BC4) entsprechend den parallelen Eingabe-Anschlüssen des zweiten integrierten Schaltkreises, als eine Zustandsanzeige der Verbindung zwischen erstem und zweitem integrierten Schaltkreis; wobei
    • die Vorrichtung ferner einen Mikrocomputer (6) für das Steuern der Übermittlung desTestmodus-Auswahlbefehlssignals und der Testdaten von der Testvorrichtung (5) und das Empfangen der resultierenden Daten durch die Testvorrichtung (5) und eine bidirektionale externe Busschnittstelle (3) für das Herstellen der Kommunikation zwischen dem Mikrocomputer und der Testvorrichtung umfasst.
  9. Vorrichtung nach Anspruch 8, wobei erster und zweiter integrierter Schaltkreis (IC1, IC2) jeweilige Chip-Auswahl-Anschlüsse (CS) für das Freigeben des ersten und zweiten integrierten Schaltkreises umfassen und die Vorrichtung Mittel für das Zuführen eines Freigabesignals zu den jeweiligen Chip-Auswahl-Anschlüssen von erstem und zweitem integrierten Schaltkreis umfasst.
  10. Vorrichtung nach Anspruch 8, wobei der Mikrocomputer (6) betriebsbereit ist, um die Mittel für das Setzen von erstem und zweitem integrierten Schaltkreis in den Testmodus zu steuern, das die Mittel zum Zuführen von Testdaten zu dem seriellen Eingabe-Anschluss des ersten integrierten Schaltkreises zu steuern und die Mittel für das Vergleichen zu steuern.
  11. Vorrichtung nach Anspruch 8, wobei die Diskriminierungs-Schaltungen (8) von erstem und zweitem integrierten Schaltkreis (IC1, IC2) betriebsbereit sind, den ersten und den zweiten integrierten Schaltkreis in den Testmodus zu setzen, wenn ein Testmodus-Auswahlbefehl an den jeweiligen seriellen Eingabe-Anschlüssen von erstem und zweitem integrierten Schaltkreis empfangen wird, und das Mittel für das Setzen von erstem und zweitem integrierten Schaltkreis in den Testmodus Mittel für das Zuführen des Testmodus-Auswahlbefehls an den seriellen Eingabe-Anschluss von erstem und zweitem integrierten Schaltkreis umfasst.
  12. Vorrichtung nach Anspruch 11, wobei die Diskriminierungs-Schaltung (8) des ersten integrierten Schaltkreises (IC1) den ersten integrierten Schaltkreis veranlasst, die Testdaten, die seinem seriellen Eingabe-Anschluss in seinen Boundary-Scan-Zellen zugeführt werden, nur dann seriell zu speichern, wenn der Testmodus-Auswahlbefehl seinem seriellen Eingabe-Anschluss zugeführt wird.
  13. Vorrichtung nach Anspruch 8, die ferner Mittel für das Zuführen von zweiten Testdaten zu dem seriellen Eingabe-Anschluss des zweiten integrierten Schaltkreises umfasst, und wobei der zweite integrierte Schaltkreis betriebsbereit ist, die zweiten Testdaten in seinen Boundary-Scan-Zellen seriell zu speichern, wenn die parallelen Daten, die in seinen Boundary-Scan-Zellen gespeichert sind, seriell als Ausgabe-Testdaten von seinem seriellen Ausgabe-Anschluss zugeführt werden.
  14. Vorrichtung nach Anspruch 13, wobei der zweite integrierte Schaltkreis (IC2) betriebsbereit ist, um die zweiten Testdaten, die in seinen Boundary-Scan-Zellen gespeichert sind, als zweite parallele Daten von seinem parallelen Daten-Eingabe/Ausgabe-Anschluss zuzuführen.
  15. Vorrichtung nach Anspruch 14, die ferner einen dritten integrierten Schaltkreis (IC3) umfasst, der einen parallelen Daten-Eingabe/Ausgabe-Anschluss (PI/PO), serielle Eingabe- (SI) und Ausgabe- (SO) Anschlüsse aufweist; und Mittel, die die Boundary-Scan-Zellen, die dem parallelen Daten-Eingabe/Ausgabe-Anschluss des dritten integrierten Schaltkreises an seinem parallelen Daten-Eingabe/Ausgabe-Anschluss zugeordnet sind, mit dem parallelen Daten-Eingabe/Ausgabe-Anschluss des zweiten integrierten Schaltkreises (IC2) verbinden; und wobei

       der dritte integrierte Schaltkreis (IC3) betriebsbereit ist, um in seinen Boundary-Scan-Zellen die zweiten parallelen Daten zu speichern, die seinem parallelen Daten-Eingabe/Ausgabe-Anschluss von dem parallelem Daten-Eingabe/Ausgabe-Anschluss des zweiten integrierte Schaltkreises (IC2) zugeführt werden, und die zweiten parallelen Daten, die in den Boundary-Scan-Zellen des dritten integriertes Schaltkreises gespeichert sind, als zweite Ausgabe-Testdaten von seinem seriellen Ausgabe-Anschluss seriell zuzuführen, und die Vorrichtung ferner umfasst:
    • zweite Vergleichsmittel für das Vergleichen der zweiten Ausgabe-Testdaten, die von dem seriellem Ausgabe-Anschluss des dritten integrierten Schaltkreises (IC3) zugeführt werden, mit den zweiten Testdaten, die dem seriellen Eingabe-Anschluss des zweiten integrierten Schaltkreises (IC2) zugeführt werden, als eine Zustandsanzeige der Verbindung zwischen zweitem und drittem integrierten Schaltkreis.
Anspruch[en]
  1. A method of testing a connection condition between input and output terminals of first (IC1) and second (IC2) adjacent integrated circuits each including a plurality of parallel data input/output terminals (PI/P0), serial input (SI) and serial output (SO) terminals, a clock terminal (SCK), a chip select terminal (CS) and boundary scan cells (BC1-BC8) corresponding to said plurality of parallel data input/output terminals, and wherein data are communicated between the parallel output terminals (PO) of said first integrated circuit and the parallel input terminals (PI) of said second integrated circuit, each of said first and second integrated circuits (IC1, IC2) comprising a discriminating circuit (8) for discriminating the presence or absence of a test mode select command for setting the first and second integrated circuits (IC1, IC2) to a test mode; said method comprising the steps of:
    • setting a mode in which a connection condition between the first and second integrated circuits is to be checked by means of the discriminating circuit (8) by transmitting a command from a testing apparatus (5) to a microcomputer (6) by way of an external bus interface (3);
    • inputting predetermined test data from said serial input terminal (SI) of said first integrated circuit (IC1) under control of the microcomputer (6) when said first integrated circuit is in said test mode and storing said predetermined test data in boundary scan cells (BC5-BC8) of said first integrated circuit (IC1);
    • outputting the test data from the parallel data output terminals (PO) of the first integrated circuit (IC1) to the parallel data input terminals (PI) of the second integrated circuit (IC2);
    • reading out the test data received from the boundary scan cells (BC1-BC4) provided corresponding to said parallel data input/output terminals of said second integrated circuit (IC2);
    • sending said stored data via said external bus interface (3) to said testing apparatus under control of said microcomputer (6); and
    • comparing the test data from the boundary scan cells (BC5-BC8) corresponding to parallel output terminals of said first integrated circuit with the test data from boundary scan cells (BC1 - BC4) corresponding to parallel input terminals of said second integrated circuit as an indication of the state of said connection between said first and second integrated circuits.
  2. The method of claim 1, wherein said first and second integrated circuits (IC1, IC2) include respective chip selection terminals (CS) for enabling said first and second integrated circuits, and said method further comprises the step of providing an enable signal (ES) to said respective chip selection terminals of said first and second integrated circuits.
  3. The method of claim 1, wherein said discrimination circuits (8) of said first and second integrated circuits (IC1, IC2) are operable to set said first and second integrated circuits to said test mode when a test mode select command is received at the respective serial input terminals of said first and second integrated circuits, and said step of setting said first and second integrated circuits in said test mode is carried out by supplying said test mode select command to said serial input terminal of said first and second integrated circuits.
  4. The method of claim 3, wherein said first integrated circuit (IC1) is controlled by the discrimination circuit (8) thereof to serially store said test data supplied to its serial input terminal in said boundary scan cells only when said test mode select command is supplied to its serial input terminal.
  5. The method of claim 1, further including the step of supplying second test data to said serial input terminal of said second integrates circuit (IC2), and wherein said step of controlling said second integrated circuit includes controlling said second integrated circuit to serially store said second test data in its boundary scan cells when the parallel data stored in its boundary scan cells is serially supplied as said output test data from its serial output terminal.
  6. The method of claim 5, wherein said step of controlling said second integrated circuit (IC2) includes controlling said second integrated circuit to supply the second test data stored in its boundary scan cells as second parallel data from its parallel data input/output terminal.
  7. The method of claim 6, further comprising a third integrated circuit (IC3) having a parallel data input/output terminal (PI/PO), serial input (SI) and output (SO) terminals, and boundary scan cells associated with its parallel data input/output terminal is connected at its parallel data input/output terminal to said parallel data input/output terminal of said second integrated circuit (IC2), and said method further comprises the steps of:
    • controlling said third integrated circuit (IC3) to store in its boundary scan cells said second parallel data supplied to its parallel data input/output terminal from said parallel data input/output terminal of said second integrated circuit (IC2), and to serially supply the second parallel data stored in said boundary scan cells of said third integrated circuit as second output test data from its serial output terminal; and
    • comparing the second output test data supplied from said serial output terminal of said third integrated circuit (IC3) with said second test data supplied to said serial input terminal of said second integrated circuit (IC2) as an indication of the state of the interconnection between said second and third integrates circuits.
  8. An apparatus comprising:
    • first (IC1) and second (IC2) integrated circuits each comprising a plurality of parallel data input/output terminals (PI/PO), serial input (SI) and output (SO) terminals, a clock terminal (SCK), a chip select terminal (CS) and boundary scan cells (BC1-BC8) corresponding to said plurality of parallel data input/output terminals, and a discriminating circuit (8) for discriminating the presence or absence of a test mode select command for selectively setting the first and second integrated circuits (IC1, IC2) to a test mode, and apparatus (5, 6, 8, SW1, SO2) for testing interconnections of said first and second integrated circuits; wherein said apparatus for testing interconnections is arranged such that data are communicated between the parallel output terminals (PO) of said first integrated circuit and the parallel input terminals (PI) of said second integrated circuit; and
    • discriminating circuits (8) in each of said first and second integrated circuits for selectively setting said first and second integrated circuits (IC1, IC2) in a test mode in which a connection condition between the first and second integrated circuits (IC1, IC2) is to be checked;
    • a testing apparatus operable in said test mode to generate predetermined test data and said test mode select command and to supply said data to said serial input terminal (SI) of said first integrated circuit (IC1); wherein
    • said first integrated circuit (IC1) is operable in said test mode to serially store said test data in its boundary scan cells and to supply the test data stored in its boundary scan cells as parallel data from said first integrated circuit at its parallel data output terminals to said second integrated circuit at its parallel data input terminals; and
    • said second integrated circuit is operable in said test mode to store in its boundary scan cells said parallel data supplied to its parallel data input terminals from said parallel data output terminals of said first integrated circuit; and
    • means (5, 6) for comparing the test data from the boundary scan cells (BC5-BC8) corresponding to the parallel output terminals of the first integrated circuit with the test data from boundary scan cells (BC1 - BC4) corresponding to the parallel input terminals of the second integrated circuit as an indication of the state of said interconnection between said first and second integrated circuits;
    • the apparatus further comprising a microcomputer (6) for controlling transmission of the test mode select command signal and the test data from said testing apparatus (5) and reception of the resulting data by said testing apparatus (5), and a bidirectional external bus interface (3) for establishing communication between said microcomputer and said testing apparatus.
  9. The apparatus of claim 8, wherein said first and second integrated circuits (IC1, IC2) include respective chip selection terminals (CS) for enabling said first and second integrated circuits, and said apparatus comprises means for providing an enable signal to said respective chip selection terminals of said first and second integrated circuits.
  10. The apparatus of claim 8, wherein the said microcomputer (6) is operable to control said means for setting said first and second integrated circuits in said test mode, control said means for supplying test data to said serial input terminal of said first integrated circuit, and control said means for comparing.
  11. The apparatus of claim 8, wherein said discrimination circuits (8) of said first and second integrated circuits (IC1, IC2) are operable to set said first and second integrated circuits to said test mode when a test mode select command is received at the respective serial input terminals of said first and second integrated circuits, and said means for setting said first and second integrated circuits in said test mode includes means for supplying said test mode select command to said serial input terminal of said first and second integrated circuits.
  12. The apparatus of claim 11, wherein said discrimination circuit (8) of said first integrated circuit (IC1) causes said fust integrated circuit to serially store said test data supplied to its serial input terminal in its boundary scan cells only when said test mode select command is supplied to its serial input terminal.
  13. The apparatus of claim 8, further comprising means for supplying second test data to said serial input terminal of said second integrated circuit, and whereinsaid second integrated circuit is operable to serially store said second test data in its boundary scan cells when the parallel data stored in its boundary scan cells is serially supplied as said output test data from its serial output terminal.
  14. The apparatus of claim 13, wherein said second integrated circuit (IC2) is operable to supply the second test data stored in its boundary scan cells as second parallel data from its parallel data input/output terminal.
  15. The apparatus of claim 14, further comprising a third integrated circuit (IC3) having a parallel data input/output terminal (P1/PO), serial input (SI) and output (SO) terminals; and means connecting boundary scan cells associated with the parallel data input/output terminal of said third integrated circuit at its parallel data input/output terminal to said parallel data input/output terminal of said second integrated circuit (IC2), and wherein

       said third integrated circuit (IC3) is operable to store in its boundary scan cells said second parallel data supplied to its parallel data input/output terminals from said parallel data input/output terminal of said second integrated circuit (IC2), and to serially supply the second parallel data stored in said boundary scan cells of said third integrated circuit as second output test data from its serial output terminal and, said apparatus further comprises:
    • second comparing means for comparing the second output test data supplied from said serial output terminal of said third integrated circuit (IC3) with said second test data supplied to said serial input terminal of said second integrated circuit (IC2) as an indication of the state of the interconnection between said second and third integrated circuits.
Anspruch[fr]
  1. Procédé de test de la condition d'une connexion entre des bornes d'entrée et de sortie de premier (IC1) et deuxième (IC2) circuits intégrés adjacents comprenant chacun une pluralité de bornes d'entrée/sortie de données parallèles (PI/PO), des bornes d'entrée (SI) et de sortie (SO) de données en série, une borne de signaux d'horloge (SCK), une borne de sélection de puce (CS) et des cellules de balayage de limites (BC1 à BC8) correspondant à ladite pluralité de bornes d'entrée/sortie de données parallèle, et dans lequel des données sont communiquées entre les bornes de sortie de données parallèles (PO) dudit premier circuit intégré et les bornes d'entrée de données parallèles (PI) dudit deuxième circuit intégré, chacun desdits premier et deuxième circuits intégrés (IC1, IC2) comprenant un circuit de différenciation (8) pour faire la différence entre la présence ou l'absence d'un signal de commande de sélection de mode de test pour programmer les premier et deuxième circuits intégrés (IC1, IC2) dans un mode de test ; ledit procédé comprenant les étapes consistant à :
    • définir un mode dans lequel une condition de connexion entre les premier et deuxième circuits intégrés doit être vérifiée au moyen du circuit de différenciation (8) en transmettant un signal de commande depuis un dispositif de test (5) vers un micro ordinateur (6) par le biais d'une interface de bus externe (3) ;
    • entrer des données de test prédéterminées en provenance de ladite borne d'entrée de données en série (SI) dudit premier circuit intégré (IC1) sous le contrôle du micro ordinateur (6) lorsque ledit premier circuit intégré se trouve dans ledit mode de test, et stocker lesdites données de test prédéterminées dans des cellules de balayage de limites (BC5 à BC8) dudit premier circuit intégré (IC1) ;
    • délivrer en sortie les données de test depuis les bornes de sortie de données parallèle (PO) du premier circuit intégré (IC1) vers les bornes d'entrée de données parallèles (PI) du deuxième circuit intégré (IC2) ;
    • lire les données de test reçues en provenance des cellules de balayage de limites (BC1 à BC4) fournies en correspondance avec lesdites bornes d'entrée/sortie de données parallèle dudit deuxième circuit intégré (IC2) ;
    • envoyer lesdites données stockées par le biais de ladite interface de bus externe (3) vers ledit dispositif de test sous le contrôle dudit micro ordinateur (6) ; et
    • comparer les données de test en provenance des cellules de balayage de limites (BC5 à BC8) correspondant aux bornes de sortie de données parallèles dudit premier circuit intégré aux données de test en provenance des cellules de balayage de limites (BC1 à BC4) correspondant aux bornes d'entrée de données parallèles dudit deuxième circuit intégré, en tant qu'une indication de la condition de ladite connexion entre lesdits premier et deuxième circuits intégrés.
  2. Procédé selon la revendication 1, dans lequel lesdits premier et deuxième circuits intégrés (IC1, IC2) comprennent des bornes de sélection de puce respectives (CS) pour activer lesdits premier et deuxième circuits intégrés, et dans lequel ledit procédé comprend en outre l'étape consistant à envoyer un signal d'activation (ES) vers lesdites bornes de sélection de puce respectives desdits premier et deuxième circuits intégrés.
  3. Procédé selon la revendication 1, dans lequel lesdits circuits de différenciation (8) desdits premier et deuxième circuits intégrés (IC1, IC2) ont pour fonction de programmer lesdits premier et deuxième circuits intégrés dans ledit mode de test lorsqu'un signal de commande de sélection de mode de test est reçu au niveau des bornes d'entrée de données en série respectives desdits premier et deuxième circuits intégrés, et ladite étape consistant à programmer lesdits premier et deuxième circuits intégrés dans ledit mode de test est exécutée en envoyant ledit signal de commande de sélection de mode de test vers ladite borne d'entrée de données en série desdits premier et deuxième circuits intégrés.
  4. Procédé selon la revendication 3, dans lequel ledit premier circuit intégré (IC1) est contrôlé par le circuit de différenciation (8) de celui-ci pour stocker en série lesdites données de test envoyées vers sa borne d'entrée de données en série dans lesdites cellules de balayage de limites uniquement lorsque ledit signal de commande de sélection de mode de test est envoyé vers sa borne d'entrée de données en série.
  5. Procédé selon la revendication 1, comprenant en outre l'étape consistant à envoyer des deuxièmes données de test vers ladite borne d'entrée de données en série dudit deuxième circuit intégré (IC2), et dans lequel ladite étape consistant à contrôler ledit deuxième circuit intégré comprend l'étape consistant à contrôler ledit deuxième circuit intégré de façon à stocker en série lesdites deuxièmes données de test dans ses cellules de balayage de limites lorsque les données parallèles stockées dans ses cellules de balayage de limites sont envoyées en série en tant que lesdites données de test délivrées en sortie à partir de sa borne de sortie de données en série.
  6. Procédé selon la revendication 5, dans lequel ladite étape consistant à contrôler ledit deuxième circuit intégré (IC2) comprend l'étape consistant à contrôler ledit deuxième circuit intégré de façon à envoyer les deuxièmes données de test stockées dans ses cellules de balayage de limites en tant que les deuxièmes données parallèles à partir de sa borne d'entrée/sortie de données parallèles.
  7. Procédé selon la revendication 6, comprenant en outre un troisième circuit intégré (IC3) ayant une borne d'entrée/sortie de données parallèles (PI/PO), des bornes d'entrée (SI) et de sortie (SO) de données en série, et des cellules de balayage de limites associées à sa borne d'entrée/sortie de données parallèles est connecté au niveau de sa borne d'entrée/sortie de données parallèles à ladite borne d'entrée/sortie de données parallèles dudit deuxième circuit intégré (IC2), et ledit procédé comprend en outre les étapes consistant à :
    • contrôler ledit troisième circuit intégré (IC3) pour stocker dans ses cellules de balayage de limites lesdites deuxièmes données parallèles envoyées vers sa borne d'entrée/sortie de données parallèles à partir de ladite borne d'entrée/sortie de données parallèles dudit deuxième circuit intégré (IC2), et pour fournir en série les deuxièmes données parallèles stockées dans lesdites cellules de balayage de limites dudit troisième circuit intégré en tant que des deuxièmes données de test délivrées en sortie à partir de sa borne de sortie de données en série ; et
    • comparer les deuxièmes données de test délivrées en sortie à partir de ladite borne de sortie de données en série dudit troisième circuit intégré (IC3) aux dites deuxièmes données de test envoyées vers ladite borne d'entrée de données en série dudit deuxième circuit intégré (IC2) en tant qu'une indication de la condition de l'interconnexion entre lesdits deuxième et troisième circuits intégrés.
  8. Dispositif comprenant :
    • des premier (IC1) et deuxième (IC2) circuits intégrés comprenant chacun une pluralité de bornes d'entrée/sortie de données parallèles (PI/PO), des bornes d'entrée (SI) et de sortie (SO) de données en série, une borne de signaux d'horloge (SCK), une borne de sélection de puce (CS) et des cellules de balayage de limites (BC1 à BC8) correspondant à ladite pluralité de bornes d'entrée/sortie de données parallèle, et un circuit de différenciation (8) pour faire la différence entre la présence ou l'absence d'un signal de commande de sélection de mode de test pour programmer de façon sélective les premier et deuxième circuits intégrés (IC1, IC2) dans un mode de test, et un dispositif (5, 6, 8, SW1, SW2) pour tester des interconnexions desdits premier et deuxième circuits intégrés ; dans lequel ledit dispositif pour tester des interconnexions est disposé de telle façon que des données sont communiquées entre les bornes de sortie de données parallèles (PO) dudit premier circuit intégré et les bornes d'entrée de données parallèles (PI) dudit deuxième circuit intégré ; et
    • des circuits de différenciation (8) dans chacun desdits premier et deuxième circuits intégrés pour programmer de façon sélective lesdits premier et deuxième circuits intégrés (IC1, IC2) dans un mode de test, dans lequel une condition d'une connexion entre les premier et deuxième circuits intégrés (IC1, IC2) doit être vérifiée ;
    • un dispositif de test qui a pour fonction, dans ledit mode de test, de produire des données de test prédéterminées et ledit signal de commande de sélection de mode de test, et pour envoyer lesdites données vers ladite borne d'entrée de données en série (SI) dudit premier circuit intégré (IC1) ; dans lequel
    • ledit premier circuit intégré (IC1) a pour fonction, dans ledit mode de test, de stocker en série lesdites données de test dans ses cellules de balayage de limites et de fournir les données de test stockées dans ses cellules de balayage de limites en tant que des données parallèles depuis ledit premier circuit intégré au niveau de ses bornes de sortie de données parallèle vers ledit deuxième circuit intégré au niveau de ses bornes d'entrée de données parallèles ; et
    • ledit deuxième circuit intégré a pour fonction, dans ledit mode de test, de stocker dans ses cellules de balayage de limites lesdits données parallèles envoyées vers ses bornes d'entrée de données parallèles à partir desdites bornes de sortie de données parallèle dudit premier circuit intégré ; et
    • des moyens (5, 6) pour comparer les données de test en provenance des cellules de balayage de limites (BC5 à BC6) correspondant aux bornes de sortie de données parallèles du premier circuit intégré aux données de test en provenance des cellules de balayage de limites (BC1 à BC4) correspondant aux bornes d'entrée de données parallèles du deuxième circuit intégré, en tant qu'une indication de la condition de ladite interconnexion entre lesdits premier et deuxième circuits intégrés ;
    • le dispositif comprenant en outre un micro ordinateur (6) pour contrôler la transmission du signal de commande de sélection de mode de test et des données de test à partir dudit dispositif de test (5), et la réception des données ainsi obtenues par ledit dispositif de test (5), et une interface de bus externe bidirectionnelle (3) pour établir une communication entre ledit micro ordinateur et ledit dispositif de test.
  9. Dispositif selon la revendication 8, dans lequel lesdits premier et deuxième circuits intégrés (IC1, IC2) comprennent des bornes de sélection de puce respectives (CS) pour activer lesdits premier et deuxième circuits intégrés, et dans lequel ledit dispositif comprend en outre des moyens pour envoyer un signal d'activation vers lesdites bornes de sélection de puce respectives desdits premier et deuxième circuits intégrés.
  10. Dispositif selon la revendication 8, dans lequel ledit micro ordinateur (6) a pour fonction de contrôler lesdits moyens pour programmer lesdits premier et deuxième circuits intégrés dans ledit mode de test ;

       contrôler lesdits moyens de fourniture de données de test vers ladite borne d'entrée de données en série dudit premier circuit intégré ; et contrôler lesdits moyens pour comparer.
  11. Dispositif selon la revendication 8, dans lequel lesdits circuits de différenciation (8) desdits premier et deuxième circuits intégrés (IC1, IC2) ont pour fonction de programmer lesdits premier et deuxième circuits intégrés dans ledit mode de test lorsqu'un signal de commande de sélection de mode de test est reçu au niveau des bornes d'entrée de données en série respectives desdits premier et deuxième circuits intégrés, et lesdits moyens pour programmer lesdits premier et deuxième circuits intégrés dans ledit mode de test comprennent des moyens pour envoyer ledit signal de commande de sélection de mode de test vers ladite borne d'entrée de données en série desdits premier et deuxième circuits intégrés.
  12. Dispositif selon la revendication 11, dans lequel ledit circuit de différenciation (8) dudit premier circuit intégré (IC1) amène ledit premier circuit intégré à stocker en série lesdites données de test envoyées vers sa borne d'entrée de données en série dans ses cellules de balayage de limites uniquement lorsque ledit signal de commande de sélection de mode de test est envoyé vers sa borne d'entrée de données en série.
  13. Dispositif selon la revendication 8, comprenant en outre des moyens pour envoyer des deuxièmes données de test vers ladite borne d'entrée de données en série dudit deuxième circuit intégré, et dans lequel ledit deuxième circuit intégré a pour fonction de stocker en série lesdites deuxièmes données de test dans ses cellules de balayage de limites lorsque les données parallèles stockées dans ses cellules de balayage de limites sont envoyées en série en tant que lesdites données de test délivrées en sortie à partir de sa borne de sortie de données en série.
  14. Dispositif selon la revendication 13, dans lequel ledit deuxième circuit intégré (IC2) a pour fonction de fournir les deuxièmes données de test stockées dans ses cellules de balayage de limites en tant que des deuxièmes données parallèles à partir de sa borne d'entrée/sortie de données parallèles.
  15. Dispositif selon la revendication 14, comprenant en outre un troisième circuit intégré (IC3) comprenant une borne d'entrée/sortie de données parallèles (PI/PO), des bornes d'entrée (SI) et de sortie (SO) de données en série ; et des moyens connectant les cellules de balayage de limites associées aux bornes d'entrée/sortie de données parallèles dudit troisième circuit intégré au niveau de sa borne d'entrée/sortie de données parallèles à ladite borne d'entrée/sortie de données parallèles dudit deuxième circuit intégré (IC2), et dans lequel ledit troisième circuit intégré (IC3) a pour fonction de stocker dans ses cellules de balayage de limites lesdites deuxièmes données parallèles envoyées vers sa borne d'entrée/sortie de données parallèles à partir de ladite borne d'entrée/sortie de données parallèles dudit deuxième circuit intégré (IC2), et pour fournir en série les deuxièmes données parallèles stockées dans lesdites cellules de balayage de limites dudit troisième circuit intégré en tant que des deuxièmes données de test délivrées en sortie à partir de sa borne de sortie de données en série et, dans lequel ledit dispositif comprend :
    • des deuxièmes moyens de comparaison pour comparer les deuxièmes données de test délivrées en sortie à partir de ladite borne de sortie de données en série dudit troisième circuit intégré (IC3) aux dites deuxièmes données de test envoyées vers ladite borne d'entrée de données en série dudit deuxième circuit intégré (IC2) en tant qu'une indication de la condition de l'interconnexion entre lesdits deuxième et troisième circuits intégrés.






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