This invention relates to interfacing one or more devices,
such as processors, with an external memory via a single bus arbiter.
In order to speed up access to FLASH memory, a page-mode
or burst-mode has been developed in which an initial access incorporates multiple
consecutive memory address codes so as to read out a block of data into a register
which is then accessed incrementally in subsequent accesses until all of the data
has been accessed, at which time, the process can be repeated. This is disclosed
in the patent US6216180. The advantage of the burst-mode is that each subsequent
access can be much shorter than the initial access, typically, 30nS for 16 bits
compared with 70nS for initially accessing a block of 128 bits. Burst-mode access
is illustrated in Figure 1 in which an initial access has an address code N and
subsequent accesses have address codes N+1, N+2 and N+3. This data burst is then
followed by a second data burst with address codes in the range M.
Burst-mode access makes use of the fact that a processor
executes code in a linear fashion to produce consecutive address codes so that once
submitted in an initial access, this need not be repeated in subsequent accesses,
which can therefore be shorter. However it follows that if the processor does not
access all of the data in subsequent accesses, perhaps because it instead requires
data at other addresses, then the benefit of fast access is reduced because of more
frequent longer initial accesses.
Furthermore sharing of a FLASH memory using burst-mode
access between multiple processors presents problems which make its use impractical
in some circumstances. Thus, for example, multiple embedded processors in an ASIC
would beneficially access a single external FLASH memory via a single bus arbiter
which determines priority of access between the processors. The use of a single
FLASH memory rather than multiple memories, reduces cost, and the number of pins
required at the interface connection between the ASIC and memory is kept to a minimum.
However, if burst-mode access is used for one or more of the processors, and the
benefit is to be maximised by preventing interruption of a burst by other processors,
then the latency of access of other processors is increased. There is therefore
a compromise between the effective use of burst-mode access by one processor and
the latency of access suffered by others. This is exacerbated when individual processors
require a higher priority of access, and disrupt burst-mode access by other processors,
without necessarily using burst-mode access themselves. This problem becomes worse
if higher priority processors are also required to run at a higher effective MIPS
Figure 2 illustrates burst-mode access by a first processor
over an address range N which is interrupted by higher priority accesses from a
second processor over an address range M. The initial access N is followed by a
subsequent access N+1, but before subsequent accesses in the address range N can
be completed, access is given to the higher priority access M for the second processor.
Once this access is completed, access is restored for the first processor, but this
has to start again with a longer initial access N+2 before a subsequent access N+3
is completed. The second processor then again interrupts with an access M+1 because
of its higher priority, before access is again restored to the first processor with
N+4 and N+5. Effective use of the burst-mode for the address range N is therefore
frustrated by the accesses for the higher priority address range M, and the address
range M cannot itself make use of the burst-mode, even though the address codes
M and M+1 are consecutive addresses. The average data throughput is therefore severely
compromised, approaching the worst case of maximum access time for every access
from every processor.
An object of the present invention is to provide a method
of interfacing one or more processors with an external memory via single bus arbiter
so as to reduce or overcome some of the above problems.
This is achieved according to one aspect of the invention
by arranging that the arbiter identifies the processor or other device associated
with each access to the memory, and that the memory has multiple block read registers
which are selected according to the identity of the processor or other device associated
with each access.
The memory can therefore support multiple burst-mode accesses
in parallel by holding burst data associated with each in a separate block read
register, and reading data from each register according to the processor identified
in each access submitted by the arbiter.
The number of block read registers need not necessarily
be equal to the number of processors. If there are fewer registers than processors,
then the arbiter may share one or more of the block read registers between particular
processors, which are preferably selected as having lower bandwidth requirements.
If there are more registers than processors, then the arbiter may use two or more
registers to support two or more address code ranges or data bursts from a single
processor. As an example, this could effectively separate code and data accesses
where these occur contiguously at different address range.
According to another aspect, the invention consists in
a method of interfacing a processor or other device with an external memory via
a single bus arbiter, in which the arbiter identifies a range of memory address
codes for each access to the memory, and the memory has multiple block read registers
which are selected according to the identity of the range of address codes associated
with each access.
The invention will now be described by way of example with
reference to the accompanying drawings in which:
Figure 1 illustrates normal burst-mode access between a single processor
and an external FLASH memory;
Figure 2 shows how two processors might access an external FLASH memory via
a bus arbiter;
Figure 3 is a schematic diagram of one embodiment of the invention;
Figure 4 shows how the bus arbiter controls accesses by the multiple processors
to the external FLASH memory in the embodiment of Figure 3.
Figure 3 shows a system-on-chip ASIC which incorporates
three processor cores A, B and C and a bus arbiter. The bus arbiter is connected
through a multiple pin interface I with an external FLASH memory device F. The FLASH
memory device F incorporates a burst-mode access mechanism and three block read
registers R1, R2 and R3 with a binary coded selection system, for example two wires
would allow selection of up to four separate block read registers.
The processors A, B and C submit access requests to the
bus arbiter S, which arbitrates according to predetermined priorities in giving
access to the FLASH memory F over the interface I. The bus arbiter identifies the
processor which is being given access and this is communicated to the FLASH memory
device so that the processor is associated with the particular block read register
which is selected for accessing data in the FLASH memory. Thus, in this example,
each of the block read registers R1, R2 and R3 could be selected to give FLASH memory
access to a corresponding processor A, B and C. The identity of the processors is
preferably binary coded, and may for example use the A  address signal, not normally
used in word-based FLASH devices.
Because the FLASH memory can support burst-mode access,
each of the block read registers can hold a data burst to support multiple accesses
at consecutive addresses which may be incremented or decremented. This data can
be read out of the registers and passed back to the respective processors under
the control of the bus arbiter. Therefore, data passing over the interface is interleaved
as between the different block read registers, but this does not detract from the
efficiency of the burst-mode access, which is preserved by the data being stored
separately in each block read register. The bus arbiter S therefore simply arbitrates
on the basis of the predetermined priorities without concern for reducing efficiency
by interrupting burst-mode access.
The manner in which two processors access respective data
bursts which are set up initially in separate block read registers is shown in Figure
4. The one data burst is set up by an initial access N and the other by an initial
access M, and although the data burst M interrupts the data burst N, the subsequent
accesses N+1 to N+5 and M+1 all benefit from being short access periods.
It will be appreciated that the changes to the bus arbiter
which are made according to the invention, will not prevent it from operating in
the standard mode if it is connected to a standard external FLASH memory with a
single block read register.
Also, it will be appreciated that, although the invention
has been described in relation to access to a FLASH memory, it is equally applicable
to access to external RAM.
Finally, although the identity of a processor or other
device accessing the memory may be fixed, it is also possible to assign an access
identity to a device based on a programmable address range. Also, the identity allocation
may be changed dynamically based on system requirements. For example, instead of
a processor the device requiring access may be a Direct Memory Access DMA module.