PatentDe  


Dokumentenidentifikation EP0827271 18.05.2006
EP-Veröffentlichungsnummer 0000827271
Titel Halbleiter-Bauelement das als Gegentaktverstärker mit Eintaktausgang verbindbar ist
Anmelder Kabushiki Kaisha Kenwood, Tokio/Tokyo, JP;
Sanken Denki K.K., Niiza, Saitama, JP
Erfinder Okuma, Tatsuhiko, Yokohama-shi, Kanagawa, JP;
Miyamoto, Akira, Fusa-shi, Tokyo, JP;
Sato, Hachiro, Kawasaki-shi, Kanagawa, JP
Vertreter derzeit kein Vertreter bestellt
DE-Aktenzeichen 69735613
Vertragsstaaten DE, GB
Sprache des Dokument EN
EP-Anmeldetag 26.05.1997
EP-Aktenzeichen 971084777
EP-Offenlegungsdatum 04.03.1998
EP date of grant 05.04.2006
Veröffentlichungstag der Übersetzung europäischer Ansprüche 19.11.1998
Veröffentlichungstag im Patentblatt 18.05.2006
IPC-Hauptklasse H03F 3/30(2006.01)A, F, I, 20051017, B, H, EP
IPC-Nebenklasse H01L 27/06(2006.01)A, L, I, 20051017, B, H, EP   

Beschreibung[en]
BACKGROUND OF THE INVENTION 1. Field of the Invention

The present invention relates to a semiconductor device and more particularly to a semiconductor device having a first semiconductor device and a second semiconductor device capable of being SEPP connected, the first semiconductor device including an NPN power transistor formed on a first semiconductor substrate and the second semiconductor device including a PNP power transistor complementary to the NPN power transistor formed on a second semiconductor substrate.

2. Description of the Related Art

An output or final stage of a power amplifier uses a complementary pair of NPN and PNP power transistors SEPP (single ended push-pull) connected to output a large power. An SEPP circuit has a bias circuit for applying a bias voltage between the bases of the two power transistors. This bias voltage is set to generally the same as the total forward voltage drop between the bases and emitters of the two power transistors. Therefore, an idling current (e.g., about several tens mA for a B-class amplifier having a maximum output of several tens W) flows through the two power transistors to prevent crossover distortions of an output waveform.

The forward voltage drop VBE between the base and emitter of a power transistor has a negative temperature coefficient of about -2 to -2.5 mV/°C. If the bias voltage Vbias is maintained constant, the operating point changes as the temperature rises by heat generated by the power transistor, so that the idling current increases which causes heat generation and temperature rise. This vicious cycle (thermorunaway) may break both the power transistors. In order to avoid this, bias circuits shown in Figs. 13 and 14 have been used. The bias circuit 1 shown in Fig. 13 is of a diode type constituted of serially connected n diodes D1 to Dn and a variable resistor VR1 for adjusting a bias voltage (idling current). The bias circuit 3 shown in Fig. 14 is of a transistor type constituted of a bias transistor 2, a fixed resistor R11, a variable resistor VR2, and a fixed resistor R12. The diodes D1 to Dn and bias transistor 2 are thermally coupled to NPN and PNP power transistors 4 and 5 to effect temperature compensation of the idling current. Since the forward voltage drop VFl to VFn has the same negative temperature coefficient of about -2 to -2.5 mV/°C, the bias voltage Vbias lowers as the temperature rises, so that the idling current can be maintained constant. Furthermore, since the forward voltage drop VBE between the base and emitter of the bias transistor 2 has the same negative temperature coefficient of about -2 to -2.5 mV/°C, the bias voltage lowers as the temperature rises, so that the idling current can be maintained constant.

In Figs. 13 and 14, reference numerals 6 and 7 represent emitter resistors. The final driver stage 10 is constituted of a resistor R5, a transistor Tr5, a resistor R6, and a transistor Tr6. The drive stage 10 is connected via oscillation suppressing resistors R7 and R8 to the bias circuit 1, 3.

NPN and PNP power transistors are available in markets as discrete semiconductor devices. If NPN and PNP power transistors are SEPP connected as the final stage of a power amplifier, NPN and PNP power transistors having desired electrical characteristics are selected and fixed to a heat sink. Diodes and transistors for bias circuits are also available in markets as discrete semiconductor devices having various types of electrical characteristics. Diodes and transistors having electrical characteristics suitable for bias circuits are selected and fixed to the same heat sink as that of the power transistors to thermally couple them to the power transistors.

Fig. 15 shows an example of a wiring layout of the driver and final stages of the power amplifier using the transistor type bias circuit 3 shown in Fig. 14. Reference numeral 8 represents a heat sink, reference numeral 9 represents a printed circuit board, and reference numerals 4 and 5 represent NPN and PNP power transistors fixed to the heat sink 8, the base terminals (B) and (B'), collector terminal (C) and (C'), and emitter terminals (E) and (E') of the NPN and PNP power transistors being connected to the printed board circuit 9. The NPN and PNP power transistors each are constituted of Darlington connected transistors. Reference numerals 6 and 7 represent emitter resistors. Reference numeral 2 represents a bias transistor fixed to the heat sink 8, the base terminal (B), collector terminal (C), and emitter terminal (E) of the bias transistor being connected to the printed circuit board 9. The bias transistor 2 constitutes a bias circuit in combination with a fixed resistor R11, a variable resistor VR2, and a fixed resistor R12.

As seen from Fig. 15, since the bias transistor 2 and NPN and PNP power transistors 4 and 5 are discrete components, all of them are required to be fixed separately to the heat sink 8. Much works are therefore necessary resulting in high cost. Since the bias transistor 2 is physically remote from the base-emitter junctions of the two NPN and PNP power transistors 4 and 5, the temperature rise of the NPN and PNP power transistors 4 and 5 has a time lag until it is transmitted to the bias transistor 2. Furthermore, since the bias transistor 2 is difficult to raise its temperature to the temperatures of the NPN and PNP power transistors 4 and 5, reliable temperature compensation for the idling current is difficult and so the reliability of preventing thermorunaway is low.

Still further, since the bias transistor 2 is disposed between the NPN and PNP power transistors 4 and 5 and interconnections are made on the printed circuit board 9, the interconnections between the collector terminals (C) and (C') and emitter terminals (E) and (E') become long. Therefore, a large mount area is required, a large electromagnetic radiation is generated because of inductance of printed wires, and output distortion becomes large.

These disadvantages are also true for the diode type bias circuit.

Several semiconductor devices with ideal thermal coupling have been proposed in which an NPN or PNP power transistor and a temperature compensating and biasing circuit diode are integrally formed on the same semiconductor substrate (Japanese Patent Laid-open Publications Nos. 53-29082, 63-169764, 63-190381, and so on). Use of these semiconductor devices for an SEPP circuit may eliminate the above disadvantages.

In order to form a diode on the same semiconductor substrate as an NPN power transistor at as small cost as possible, a PN junction diode is used. However, if the device structure is made simple, parasitic transistors are inevitably formed. It is possible to use the base-emitter junction of a parasitic transistor as a diode. However, in this case, it is necessary to lower the current amplification factor hfe of the parasitic transistor as small as 1/10 or lower. The forward voltage drop of the diode at this amplification factor is about 1 V which is very different from the forward voltage drop VBE = 0.6 V between the base-emitter of a power transistor (if the power transistor is constituted of two-stage Darlington connected transistors, 2VBE = 1.2 V, and for three-stage Darlington connected transistors, 3VBE = 1.8 V).

Similar to the above, if a PN junction diode is formed on the same semiconductor substrate as a PNP power transistor, the forward voltage drop of the diode becomes very different from the forward voltage drop VBE = 0.6 V between the base-emitter of a power transistor (if the power transistor is constituted of two-stage Darlington connected transistors, 2VBE = 1.2 V, and for three-stage Darlington connected transistors, 3VBE = 1.8 V).

Therefore, even if a first semiconductor device integrating an NPN power transistor and a temperature compensating and biasing diode on the same semiconductor substrate is used in combination with a second semiconductor device integrating a PNP power transistor and a temperature compensating and biasing diode on the same semiconductor substrate, the bias voltages mismatch. Therefore, this combination cannot be applied and semiconductor makers do not manufacture and sell such semiconductor devices.

As shown in Fig. 3 of Japanese patent Laid-open Publication No. 63-169764, if a power transistor and a diode are formed on different semiconductor substrates, the forward voltage drop of the diode can be set about 0.6 V same as the forward voltage drop between the base and emitter of the power transistor. However, thermal coupling becomes imperfect and the manufacture cost rises.

From this reason, with the conventional techniques, NPN and PNP power transistors and bias circuit transistors or diodes are prepared independently and mounted separately on a heat sink. Therefore, the problems described earlier cannot be solved, the problems including complicated works in manufacturing SEPP circuits, poor temperature compensation, large mount area, and large output distortion.

EP 0 583 991 A1 discloses a device for biasing an RF device operating in quasi-linear modes with temperature compensation. To this end, a biasing device is in thermal contact with an RF device for actively biasing the RF device operating in quasi-linear modes. The biasing device provides a low impudence current source with high current capability to the base of the RF device. The biasing device includes three specially-processed transistors. The second and third transistors are connected such that their base-emitter and base-collector junctions are in parallel effectively forming two exceptionally low turn-on series diodes. The result of reducing the resistances of the second and third transistors, by configuration and processing, is that they turn on slightly before the RF device is biased to its quiescent point.

SUMMARY OF THE INVENTION

It is an object of the present invention to solve the above-described problems associated with the conventional techniques and provide a semiconductor device capable of maintaining good temperature compensation and reducing manufacture works of SEPP connecting NPN and PNP power transistors and temperature compensating and biasing circuits.

It is another object of the present invention to provide a semiconductor device which does not require a large mount area for SEPP connection and can suppress output distortion.

The semiconductor device recited in claim 1 comprises a first semiconductor device having an NPN power transistor formed on a first semiconductor substrate and a second semiconductor device having a PNP power transistor complementary to the NPN power transistor formed on a second semiconductor substrate, the first and second semiconductor devices capable of being SEPP connected, the first semiconductor device having one or a plurality of serially connected bias circuit diodes formed on the first semiconductor device, the anode side of the diode or diodes being connected to the base of the NPN power transistor and the cathode side thereof being connected to a first bias terminal, the second semiconductor device having one or a plurality of serially connected bias circuit diodes formed on the second semiconductor device, the cathode side of the diode or diodes being connected to the base of the PNP power transistor and the anode side thereof being connected to a second bias terminal, wherein the total forward voltage drop V1 of the bias circuit diode or diodes of one of the first and second semiconductor devices is set to an arbitrary constant value smaller than E exclusive of about E/2, and the bias circuit diode or diodes of the other of the first and second semiconductor devices are Schottky barrier diodes and the total forward voltage drop V2 of the bias diode or diodes is set to a predetermined value of about (E - V1), where E is a total forward voltage drop between the bases and emitters of the NPN and PNP power transistors of the first and second semiconductor devices.

The total forward voltage drop V1 of the bias circuit diode or diodes of one of the first and second semiconductor devices is set to an arbitrary constant value smaller than E exclusive of about E/2, where E is a total forward voltage drop between the bases and emitters of the NPN and PNP power transistors of the first and second semiconductor devices. It is therefore possible to form an ordinary diode such as a PN junction diode on the same semiconductor substrate as the NPN or PNP power transistor. The manufacture is therefore easy and cost effective. The bias circuit diode of the other of the first and second semiconductor devices uses a Schottky barrier diode. Therefore, the forward voltage drop per one diode can be set finely in the range from 0.1 to 0.5 V, by using relatively simple structure. The total forward voltage drop V2 of the diodes can be easily set to a predetermined value of about (E - V1). As a result, only by mounting the first and second semiconductor devices on a heat sink, the diodes of a bias circuit for generating a proper bias voltage can be automatically mounted and the assembly work of the SEPP circuit can be simplified. Since Schottky diodes are used only for one of the first and second semiconductor devices, a rise of component cost is small.

The diodes of the first and second semiconductor devices are formed on the same semiconductor substrate as the NPN or PNP power transistor. Accordingly, ideal thermal coupling can be realized and good temperature compensation can be performed.

If a combination of the complementary first and second semiconductor devices is selected, the bias circuit diodes are automatically selected so that design of the SEPP circuit is simple.

Each of the first and second semiconductor devices may be used as a conventional NPN or PNP power transistor.

In the semiconductor device recited in claim 2 depending from claim 1, a bias voltage adjusting resistor is serially connected to the bias circuit diode or diodes of the first or second semiconductor device.

The bias voltage adjusting resistor is serially connected to the bias circuit diode or diodes. Therefore, if the value of this bias voltage adjusting resistor is set to an optimum value of the bias circuit of the SEPP circuit constituted by the first and second semiconductor devices, the bias voltage adjustment can be dispensed with and the adjustment work of the bias circuit after the assembly of the SEPP circuit becomes unnecessary. In this connection, a conventional external bias circuit requires large works and long time which cause a large increase in manufacture cost. With the conventional method, after the assembly of an SEPP circuit, the temperature is raised to a predetermined value and the temperatures of the NPN and PNP power transistors and bias circuit elements are made equal to each other. Thereafter, the bias voltage adjusting resistor is adjusted to set the idling current to a predetermined rated value.

Since the number of interconnections for the bias circuit on the printed circuit board can be reduced, the mount area reduces. Therefore, the printed patterns of for the emitter and collector terminals to be formed on the printed circuit board for the SEPP connection can be shortened so that electromagnetic radiation is reduced and the generation of output distortion can be suppressed.

In the semiconductor device recited in claim 3 depending from claim 1 or 2, the first semiconductor device includes a base terminal, a collector terminal, and an emitter terminal respectively connected to the base, collector, and emitter sides of the NPN power transistor; and the second semiconductor device includes a base terminal, a collector terminal, and an emitter terminal respectively connected to the base, collector, and emitter sides of the PNP power transistor, and wherein the terminals are disposed so that when the first and second semiconductor devices are juxtaposed side by side, the emitter terminals are positioned at the most inner side and the collector terminals are positioned at the second most inner side.

The terminals are disposed so that when the first and second semiconductor devices are juxtaposed side by side, the emitter terminals are positioned at the most inner side and the collector terminals are positioned at the second most inner side. Therefore, the printed patterns of the printed circuit board for the emitter and collector terminals necessary for the SEPP connection can be made short so that electromagnetic radiation is reduced and output distortion can be suppressed.

In the semiconductor device recited in claim 4 depended from claim 3, an emitter resistor is connected between the emitter terminal and the emitter of the NPN power transistor of the first semiconductor device, and an emitter resistor is connected between the emitter terminal and the emitter of the PNP power transistor of the second semiconductor device.

Since the emitter resistor is provided to the NPN and PNP power transistors of both the first and second semiconductor devices, works and spaces for externally connecting the emitter resistors can be omitted.

In the semiconductor device recited in claim 5 depended from claim 1, an emitter resistor is connected at one end to the emitter of the NPN power transistor of the first semiconductor device, the other end thereof being connected to a second emitter terminal, and an emitter resistor is connected at one end to the emitter of the PNP power transistor of the second semiconductor device, the other end thereof being connected to a second emitter terminal, wherein when the first and second semiconductor devices are juxtaposed side by side, the second emitter terminals, are positioned more inner than emitter terminals.

One end of the built-in emitter resistor is connected to the second emitter terminal different from the emitter terminal connected to the emitter side of the power transistor. Therefore, the emitter of the power transistor can be connected directly to an external circuit without being intervened by the built-in emitter resistor. In this case, the collector current of the power transistor can be monitored by measuring a voltage across the built-in emitter resistor, or another emitter resistor may be connected externally for changing the value of the built-in emitter resistor. The second emitter terminals are positioned at the most inner side when the first and second semiconductor devices are juxtaposed side by side. Therefore, in the standard case using the built-in emitter resistors, the second emitter terminals can be interconnected by a shortest distance on the printed circuit board so that the length of the printed pattern for the loudspeaker output can be made shortest.

In the semiconductor device recited in claim 6 depended from claim 1 or 2, the anode side of the bias circuit diode or diodes of the first semiconductor device is connected to a base terminal, a base resistor being connected between the anode side and the base of the NPN power transistor, and the cathode side of the bias circuit diode or diodes of the second semiconductor device is connected to a base terminal, and a base resistor being connected between the cathode side and the base of the PNP power transistor.

The amount of current flowing through the resistor connected between the driver stage and the bases of the NPN and PNP power transistors for the oscillation suppression can be reduced and the voltage loss across the oscillation suppressing resistor can be reduced. As a result, an output of the power amplifier constituted of the first and second semiconductor devices SEPP connected can be increased. If the oscillation suppressing base resistor is built in the first and second semiconductor devices, works and spaces required for externally connecting oscillation suppressing inflammable resistors to the printed circuit board can be omitted and the cost can be lowered.

In the semiconductor device recited in claim 10 depending from claim 1 or 2, the NPN power transistor of the first semiconductor device includes Darlington connected n-stage NPN transistors, the emitter of each of n-stage NPN transistors being connected via an emitter resistor to an emitter terminal, and the PNP power transistor of the second semiconductor device includes Darlington connected n-stage PNP transistors, the emitter of each of n-stage PNP transistors being connected via an emitter resistor to an emitter terminal.

If the polarity of an input signal to the first and second semiconductor devices SEPP connected changes, for example, from plus to minus, carriers accumulated in the bases of the transistors at the second and following stages among n-stage NPN transistors can be absorbed rapidly in the bases of the transistors at the second and following stages among n-stage PNP transistors, and the n-stage NPN transistors can be cut off quickly, without passing through the last stage emitter resistor. As a result, crossover distortion is hard to be generated. Further, since a large through current is prevented from flowing through the last stage NPN transistor to the last stage PNP transistor, breakage of these last stage transistors can be avoided.

In the semiconductor device recited in claim 12 depending from claim 1 or 2, the NPN power transistor of the first semiconductor device includes Darlington connected n-stage NPN transistors, the emitter of the last stage NPN transistor being connected to a first emitter terminal and the base of each of the second and following stage NPN transistors being connected via an emitter resistor to a second emitter terminal, and the PNP power transistor of the second semiconductor device includes Darlington connected n-stage PNP transistors, the emitter of the last stage PNP transistor being connected to a first emitter terminal and the base of each of the second and following stage PNP transistors being connected via an emitter resistor to a second emitter terminal.

Similar to the semiconductor device recited in claim 10, if the polarity of an input signal to the first and second semiconductor devices SEPP connected changes, for example, from plus to minus, carriers accumulated in the bases of the transistors at the second and following stages among n-stage NPN transistors can be absorbed rapidly in the bases of the transistors at the second and following stages among n-stage PNP transistors, without passing through the last stage emitter resistor. As a result, crossover distortion is hard to be generated. Further, since a large through current is prevented from flowing through the last stage NPN transistor to the last stage PNP transistor, breakage of these last stage transistors can be avoided.

BRIEF DESCRIPTION OF THE DRAWINGS

  • Fig. 1 is a circuit diagram showing the structure of a driver stage and an output stage of a power amplifier according to a first embodiment of the invention.
  • Fig. 2 is a diagram showing interconnections of the output stage of the power amplifier shown in Fig. 1.
  • Fig. 3 is a circuit diagram showing the structure of a driver stage and an output stage of a power amplifier according to a modification of the first embodiment shown in Fig. 1.
  • Fig. 4 is a circuit diagram showing the parallel push-pull structure of first and second semiconductor devices shown in Fig. 3.
  • Fig. 5 is a circuit diagram showing the parallel push-pull structure of first and second semiconductor devices shown in Fig. 1.
  • Fig. 6 is a diagram illustrating the operation of the circuit shown in Fig. 1 in which one of variable resistors is omitted.
  • Figs. 7A and 7B are circuit diagrams showing first and second semiconductor devices according to a modification of the semiconductor device shown in Fig. 3.
  • Figs. 8A and 8B are circuit diagrams showing first and second semiconductor devices according to another modification of the semiconductor device shown in Fig. 3.
  • Figs. 9A and 9B are circuit diagrams showing first and second semiconductor devices according to still another modification of the semiconductor device shown in Fig. 3.
  • Fig. 10 is a circuit diagram showing the structure of a driver stage and an output stage of a power amplifier according to a second embodiment of the invention.
  • Fig. 11 is a diagram showing the layout of terminals of first and second semiconductor devices of the second embodiment shown in Fig. 10.
  • Fig. 12 is a circuit diagram showing the structure of a driver stage and an output stage of a power amplifier according to a modification of the second embodiment shown in Fig. 10.
  • Fig. 13 is a circuit diagram showing a power amplifier output stage having a conventional diode type bias circuit.
  • Fig. 14 is a circuit diagram showing a power amplifier output stage having a conventional transistor type bias circuit.
  • Fig. 15 is a diagram showing a layout of interconnections of the circuit shown in Fig. 14.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Fig. 1 is a circuit diagram showing the structure of a driver stage and an output stage of a power amplifier according to the first embodiment of the invention, and Fig. 2 is a diagram showing interconnections of the output stage of the power amplifier.

Reference numeral 20 represents a first semiconductor device having an NPN power transistor 21 and an ordinary PN junction diode 22 integrally formed near to each other on the same semiconductor substrate by well known semiconductor manufacture processes. The NPN power transistor 21 is constituted of Darlington connected NPN transistors Tr1 and Tr2 whose emitters are connected to one ends of stabilizing emitter resistors R1 and R2. The other end of the emitter resistor R1 is connected to the emitter of the transistor Tr2, and the other end of the emitter resistor R2 is connected to a second emitter terminal (E2) for external connection. R1 is about 100 to 200 &OHgr;, for example 150 &OHgr;, and R2 is about 0.22 to 0.47 &OHgr;, for example 0.47 &OHgr;.

The forward voltage drop VBE of the base-emitter junction of the transistors Tr1 and Tr2 is both about 0.6 V. The temperature coefficient of VBE is a negative value of &agr;1 mV/°C (&agr;1 is about -2).

The diode 22 constitutes a bias circuit of the SEPP circuit in combination with diodes of a second semiconductor device to be described later and a variable resistor. In order to make the diode 22 inexpensive, it is formed as a PN junction diode formed on the same semiconductor substrate, by inserting a P shielding region. The amplification factor hfe of the parasitic transistor is suppressed to 1/10 or smaller. Therefore, the forward voltage drop VF of the PN junction of the diode 22 is about 1V. The temperature coefficient of VF is a negative value of &agr;2 mV/°C. For the PN junction diode, &agr;2 ≈ &agr;1.

The first semiconductor device 20 has five external connection terminals, including a base terminal (B), a bias terminal (b), a collector terminal (C), a first emitter terminal (E1), and a second emitter terminal (E2). Of the NPH power transistor 21, the base (base of transistor Tr1), collector (collectors of transistors Tr1 and Tr2), and emitter (emitter of transistor Tr2) are respectively connected to the base terminal (B), collector terminal (C), and first emitter terminal (E1). The cathode of the diode 22 is connected to the base terminal (b). The anode of the diode 22 is internally connected to the base (base of transistor Tr1) of the NPN power transistor.

The second semiconductor device 30 has the structure symmetrical to the first semiconductor device 20. The second semiconductor device 30 has a PNP power transistor 31 and n Schottky barrier diodes 321 to 32n integrally formed near to each other on the same semiconductor substrate by well known semiconductor manufacture processes. The PNP power transistor 31 is constituted of Darlington connected PNP transistors Tr3 and Tr4 and has the same electrical characteristics as the NPN power transistor 21 of the first semiconductor device, to thereby form a complementary pair therewith. The emitters of the transistors Tr3 and Tr4 are connected to one ends of stabilizing emitter resistors R3 and R4. The other end of the emitter resistor R3 is connected to the emitter of the transistor Tr4, and the other end of the emitter resistor R4 is connected to a second emitter terminal (E2') for external connection. R3 has the same value as R1, for example 150 &OHgr;, and R4 has the same value as R2, for example 0.47 &OHgr;.

The forward voltage drop VBE of the base-emitter junction of the transistors Tr3 and Tr4 is both about 0.6 V. The temperature coefficient of VBE is a negative value of &agr;3 mV/°C (&agr;3 ≈ &agr;1).

The diodes 321 to 32n are serially connected in the second semiconductor device 30, and the cathode side of the diodes is internally connected to the base (base of transistor Tr3) of the PNP power transistor 31. Since these diodes 321 to 32n are Schottky barrier (metal-semiconductor junction) diodes, the forward voltage drop per one diode can be set finely in the range from 0.1 to 0.5 V, by using relatively simple structure. Therefore, the total forward voltage drop V2 of the diodes can be set freely. Although the temperature coefficients &agr;41 to &agr;4n mV/°C of the diodes 321 to 32n take a negative value, these temperature coefficients have some freedom of design near a value of -2. It is simple to set &agr;41 ≈ &agr;1 (I = 1 to n).

The following description is directed to the number n of diodes 321 to 32n, the forward voltage drops Vc1 to Vcn of the diodes 321 to 32n, the total forward voltage drop of the diodes 321 to 32n, and the temperature coefficients &agr;41 to &agr;4n.

If E is the total forward voltage drop between the bases and emitters of the NPN and PNP power transistors 21 and 31, then E = 4VBE ≈ 2.4 V where VBE is the forward voltage drop between the base and emitter of each transistor Tr1 to Tr4 and is about 0.6 V.

It is necessary to set the bias voltage Vbias of the bias circuit to generally the same value as E. If V1 is the forward voltage drop of the diode of the bias circuit of the first semiconductor device 20, V1 = 1 V. Therefore, the diodes 321 to 32n are formed to have the total forward voltage drop V2 generally the same value as (2.4 V - 1 V) = 1.4 V. In practice, V2 is set to a predetermined value slightly smaller than (E - V1) and the bias voltage capable of flowing a desired idling current is adjusted by a variable resistor VR3 to be described later.

The temperature coefficient A of the total forward voltage drop E between the bases and emitters of the NPN and PNP power transistors 21 and 31 is 2 (&agr;1 + &agr;3), and the temperature coefficient of the forward voltage drop V1 of the bias circuit of the first semiconductor device 20 is &agr;2. Therefore, if B is the temperature coefficient of the total forward voltage drop V2 of the diodes 321 to 32n of the bias circuit of the second semiconductor device 30, then B = ( A - &agr; 2 ) ,  i . e . , &agr; 41 + &agr; 42 + ... + &agr; 4 n = 2 ( &agr; 1 + &agr; 3 ) - &agr; 2......

The forward voltage drops VG1 to VGn of the diodes 32l to 32n may be the same for some of them or may be different for all of them. The temperature coefficients &agr;41 to &agr;4n of VG1 to VGn may be the same for some of them or may be different for all of them.

For example, if the forward voltage drops VG1 to VGn of the diodes 32l to 32n are all the same and the temperature coefficients &agr;41 to &agr;4n of VG1 to VGn are all the same, then in the range of 0.1 V ≤VGi ≤ 0.5 V V G i 1.4 / n &agr; 4 i ( 2 &agr; 1 + 2 &agr; 3 &agr; 2 ) / n where i = 1 n If n = 3 and &agr;1 = &agr;3 = &agr;2, then VGi ≈ 1.4/3V and &agr;4i ≈ &agr;1.

The second semiconductor device 30 has five external connection terminals, including a base terminal (B'), a bias terminal (b'), a collector terminal (C'), a first emitter terminal (E1'), and a second emitter terminal (E2'). Of the PNP power transistor 31, the base (base of transistor Tr3), collector (collectors of transistors Tr3 and Tr4), and emitter (emitter of transistor Tr4) are respectively connected to the base terminal (B'), collector terminal (C'), and first emitter terminal (E1'). The cathode side of the serially connected diodes 321 to 32n is connected to the base terminal (b').

As shown in Fig. 2, the connection terminals of the first and second semiconductor devices 20 and 30 are symmetrical to each other when they are juxtaposed side by side. The second emitter terminals (E2) and (E2'), first emitter terminals (E1) and (E1'), collector terminals (C) and (C'), bias terminals (b) and (b'), and base terminals (B) and (B') are disposed in this order from the inner side to the outer side.

As shown in Fig. 2, for the SEPP connection of the power amplifier using the first and second semiconductor devices 20 and 30, these devices 20 and 30 are mounted on the same principal plane of a heat sink 40, being juxtaposed side by side. The connection terminals (B), (b), (C), (E1), (E2), (B'), (b'), (C'), (E1'), and (E2') are connected to corresponding terminals of a printed circuit board 41. If the emitter resistors to be used are R2 connected between the first and second emitter terminals (E1) and (E2) and R4 connected between the first and second emitter terminals (E1') and (E2'), the second emitter terminals (E2) and (E2') are connected together by a printed pattern 42 for a loudspeaker terminal (SP). Since the bias circuit diode is not necessary to be connected between the first and second semiconductor devices 20 and 30 mounted on the heat sink 40 and since the first and second semiconductor devices 20 and 30 are disposed symmetrically, the second emitter terminals (E2) and (E2') are positioned nearest. Therefore, they can be interconnected by a shortest distance and the printed pattern 42 is not necessary to be made long.

Printed patterns 43 and 44 for +Vcc and -Vcc adjacent to the printed pattern 42 connect +Vcc to the collector terminal (C) of the first semiconductor device 20 and -Vcc to the collector terminal (C') of the second semiconductor device 30. Since the collector terminals (C) and (C') are also positioned relatively adjacent to each other, the printed pattern 44 is not necessary to be made long.

As compared to the conventional semiconductor device shown in Fig. 15, the mount area of the printed circuit board is considerably reduced by a half or more. It is therefore possible to make the amplifier compact, and electromagnetic radiation is also reduced so that output distortion can be suppressed greatly.

Furthermore, works and spaces for externally connecting the emitter resistors R2 and R4 can be omitted.

A circuit for monitoring a collector current flowing through the NPN power transistor 20 or PNP power transistor 30 may be connected to the first emitter terminal (E1) or (E1'), the circuit monitoring the collector current by measuring a voltage relative to the printed pattern 42. If the built-in emitter resistors R2 and R4 of the first and second semiconductor device 20 and 30 are to be changed to new values, resistors are connected between the first emitter terminal (E1) and the second emitter terminal (E2) and between the second emitter terminal (E1') and the second emitter terminal (E2').

As shown in Fig. 1, a final stage transistor Tr5 of the drive stage 10 and a resistor R5 are connected via an oscillation suppressing resistor R7 between the base terminal (B) of the first semiconductor device 20 and +Vcc, whereas a final stage transistor Tr6 of the drive stage 10 and a resistor R6 are connected via an oscillation suppressing resistor R8 between the base terminal (B') of the second semiconductor device 30 and -Vcc. The values of the resistors R7 and R8 are about several &OHgr; to several hundreds &OHgr;, for example 47 &OHgr;. In combination with the coupling capacitance CCB between the collectors and bases of the transistors Tr1 and Tr3, the resistors R7 and R8 lower the gain in the high frequency band to suppress oscillation.

A variable resistor VR3 for bias voltage adjustment (idling current adjustment) is connected via printed patterns 45 and 46 between the bias terminal (b) of the first semiconductor device 20 and the bias terminal (b') of the second semiconductor device 30. A bias circuit 50 is constituted of the diode of the first semiconductor device 20 and variable resistor VR3, and diodes 321 to 32n.

The variable resistor VR3 absorbs a variation of the characteristics of the first and second semiconductor devices 20 and 30 by setting the idling current to a predetermined value. In this embodiment, the diode 22 is formed on the same semiconductor substrate as the NPN power transistor 21 and the temperatures of the diode 22 and NPN power transistor 21 are always the same, and the diodes 321 to 32n are also formed on the same semiconductor substrate as the PNP power transistor 31 and the temperatures of the diodes and PNP power transistor are always the same. As a result, in adjusting the idling current by raising the temperature to a predetermined value, this adjustment work can be executed without waiting until the temperatures of the NPN power transistor 21 and diode 22 or the PNP power transistor and diodes 321 to 32n become the same. Alternatively, the adjustment work can be executed without raising the temperature to the predetermined value. Accordingly, the adjustment time can be shortened greatly.

The total forward voltage drop of the diodes 22 and 321 to 32n is generally the same as the total forward voltage drop of the NPN and PNP power transistors 21 and 31 and the combined temperature coefficients are generally the same. Therefore, the idling current after adjustment becomes generally constant irrespective of the temperature change.

According to this embodiment, as the first and second semiconductor devices 20 and 30 having the matched electrical characteristics are SEPP connected, mounting the bias circuit diodes is automatically completed, reducing the amount of assembly work. The forward voltage drop of the diode of the first semiconductor device 20 may take an arbitrary value excepting about E/2. Therefore, an ordinary PN junction diode can be used. Since the Schottky barrier diodes are formed only in the second semiconductor device 30, the component cost can be reduced correspondingly.

In the first semiconductor device 20, the diode 22 formed on the same semiconductor substrate as the NPN power transistor catches a temperature rise of the NPN power transistor at the nearest distance, and changes its temperature characteristics cancelling out the temperature rise. In the second semiconductor device 30, the diodes 321 to 32n formed on the same semiconductor substrate as the PNP power transistor catch a temperature rise of the PNP power transistor at the nearest distance, and change their temperature characteristics cancelling out the temperature rise. Accordingly, ideal thermal coupling can be realized and good temperature compensation can be performed.

If a combination of the complementary first and second semiconductor devices 20 and 30 is selected, the bias circuit diodes are automatically selected so that design of the SEPP circuit is simple. Each of the first and second semiconductor devices 20 and 30 may be used as a conventional NPN or PNP power transistor.

The connection terminals are disposed so that when the first and second semiconductor devices 20 and 30 are juxtaposed side by side, the first emitter terminals (E1) and (E1') and second emitter terminals (E2) and (E2') are positioned at the most inner side, and the collector terminals (C) and (C') are positioned at the second most inner side. Therefore, the printed patterns of the printed circuit board for the emitter and collector terminals necessary for the SEPP connection can be made short so that electromagnetic radiation is reduced and output distortion can be suppressed.

Since the emitter resistors R2 and R4 of the NPN and PNP power transistors are built in the first and second semiconductor devices 20 and 30, works and spaces for mounting the emitter resistors on the printed circuit board can be omitted.

One ends of the built-in emitter resistors R2 and R4 are connected to the second emitter terminals (E2) and (E2') different from the first emitter terminals (E1) and (E1'). Therefore, the emitter of the power transistor can be connected directly to an external circuit without being intervened by the built-in emitter resistor. In this case, the collector current of the power transistor can be monitored by measuring a voltage across the built-in emitter resistor, or another emitter resistor may be connected externally for changing the value of the built-in emitter resistor. The second emitter terminals (E2) and (E2') are positioned at the most inner side when the first and second semiconductor devices 20 and 30 are juxtaposed side by side. Therefore, in the standard case using the built-in emitter resistors, the second emitter terminals (E2) and (E2') can be interconnected by a shortest distance on the printed circuit board 41 so that the length of the printed pattern for the loudspeaker output can be made shortest.

In the above embodiment, the variable resistor VR3 is connected externally. Instead, if a variation of the electrical characteristics of the first and second semiconductor devices is small, the variable resistor VR3 may be replaced by a fixed resistor suitable for setting an optimum bias voltage. This fixed resistor may be formed in the first or second semiconductor device and serially connected to the diodes. Furthermore, if the characteristics of the diodes of the first and second semiconductor devices are set to optimum values of the bias circuit, the fixed resistor itself can be omitted. In this manner, the bias voltage adjustment can be dispensed with and the adjustment work of the bias circuit after the assembly of the SEPP circuit becomes unnecessary. In this connection, a conventional external bias circuit requires large works and long time which cause a large increase in manufacture cost. With the conventional method, after the assembly of an SEPP circuit, the temperature is raised to a predetermined value and the temperatures of the NPN and PNP power transistors and bias circuit elements are made equal to each other. Thereafter, the bias voltage adjusting resistor is adjusted to set the idling current to a predetermined rated value.

Since the number of interconnections for the bias circuit on the printed circuit board can be reduced, the mount area reduces. Therefore, the printed patterns of for the emitter and collector terminals to be formed on the printed circuit board for the SEPP connection can be shortened so that electromagnetic radiation is reduced and the generation of output distortion can be suppressed.

The diode of the first semiconductor device may be a plurality of serially connected diodes, and the diodes of the second semiconductor device may use a single diode. Further, an ordinary diode may be formed in the second semiconductor device, and Schottky barrier diodes may be formed in the first semiconductor device.

The diodes of the first and second semiconductor devices have both the negative temperature coefficient of the forward voltage drop. Therefore, the conditions given by the equation are not necessary to be strictly satisfied, but if the relationship approximate to the equation (1) is satisfied, the temperature compensation near ideal state is possible.

Fig. 3 is a circuit diagram of a driver stage and an output stage of a power amplifier according to a modification of the first embodiment shown in Fig. 1.

In the embodiment shown in Fig. 1, the resistors R7 and R8 are connected between the final stage transistors Tr5 and Tr6 of the driver stage 10 and the bias circuit 50. In this modification shown in Fig. 3, an oscillation suppressing base resistor R7' is formed between the anode of the diode 22 and the base of the transistor Tr1 on the same semiconductor substrate as that of the NPN power transistor 21 and diode 22 of a first semiconductor device 200, and another oscillation suppressing base resistor R8' is formed between the cathode side of the diodes 321 to 32n and the base of the transistor Tr3 on the same semiconductor substrate as that of the PNP power transistor 31 and diodes 321 to 32n of a second semiconductor device 300. The values of the base resistors R7' and R8' are about several &OHgr; to several hundreds &OHgr;, for example, 47 &OHgr;.

In combination with the coupling capacitance CCB between the collectors and bases of the transistors Tr1 and Tr3, the base resistors R7' and R8' lower the gain in the high frequency band to suppress oscillation.

In the embodiment shown in Fig. 1, the emitter resistor R1 of the transistor Tr1 of the NPN power transistor 21 is connected between the emitters of the transistors Tr1 and Tr2, and the emitter resistor R3 of the transistor Tr3 of the PNP power transistor 31 is connected between the emitters of the transistors Tr3 and Tr4. In the modification shown in Fig. 3, the emitter resistor R1' of the transistor Tr1 is connected between the emitter of the transistor Tr1 and the second emitter terminal (E2), and the emitter resistor R3' of the transistor Tr3 is connected between the emitter of the transistor Tr3 and the second emitter terminal (E2'). The values of the resistors R1' and R3' are for example 150 &OHgr;.

The other structures are the same as Fig. 1. The layout of the connection terminals of the first and second semiconductor devices 200 and 300 shown in Fig. 3 is the same as the first and second semiconductor devices 20 and 30 (refer to Fig. 2).

As shown in Fig. 1, the oscillation suppressing resistors R7 and R8 are connected between the final stage transistors Tr5 and Tr7 and the base circuit 50. In this case, works and spaces are required for mounting and connecting the oscillation suppressing resistors R7 and R8 to the printed circuit board 41. It is necessary for the safety purpose to use inflammable resistors as the resistors R7 and R8 connected to the printed circuit board 41. This inflammable resistor raises the cost. Since the base current of the transistor Tr1 as well as the bias current of the bias circuit 50 flows through the resistor R7, the voltage loss becomes large and an output voltage of the power amplifier lowers.

In contrast, in the modification shown in Fig. 3, the oscillation suppressing resistors R7' and R8' are built in the first and second semiconductor devices 200 and 300. Therefore, by mounting the first and second semiconductor devices 200 and 300 on the heat sink 8, the oscillation suppressing resistors R7' and R8' are automatically assembled and it is not necessary to externally connect expensive inflammable resistors for oscillation suppression. Works and spaces for externally connecting such resistors on the printed circuit board can be dispensed with and the cost can be lowered.

Since the bias current will not flow through the resistors R7' and R8', the amount of current reduces and the voltage loss at the resistors R7' and R8' lowers. An output of the power amplifier can therefore be increased.

In the case of the parallel push-pull structure such as shown in Fig. 4 in which a first output stage 11A constituted of SEPP connected first and second semiconductor devices 200A and 300A is connected in parallel with a second output stage 11B constituted of SEPP connected first and second semiconductor devices 200B and 300B, on the output side of the driver stage 10, the variable resistor VR3 of the bias circuit is provided only to the first output stage 11A (both ends of the variable resistor VR3 are connected to the bias terminal (b) of the first semiconductor device 200A and the bias terminal (b') of the second semiconductor device 300A). In the second output stage 11B, the bias terminal (b) of the first semiconductor device 200B is connected to the base terminal (B), i.e., the diode 22 being shorted, and the bias terminal (b') of the second semiconductor device 300B is connected to the base terminal (B'), i.e., the diodes 321 to 32n being shorted. In this manner, a same proper bias voltage can be applied to the first and second output stages 11A and 11B so that only one variable resistor VR3 is sufficient.

In contrast, if the first and second semiconductor devices 20 and 30 shown in Fig. 1 are used for configuring the parallel push-pull structure, as shown in Fig. 5, a first output stage 11C constituted of SEPP connected first and second semiconductor devices 20A and 30A is connected in parallel with a second output stage 11D constituted of SEPP connected first and second semiconductor devices 20B and 30B, via oscillation suppressing resistors R70, R80, R71, and R81. In this case, in order to apply a same proper bias voltage to the first and second output stages 11C and 11D, it is necessary to provide the first and second output stages 11C and 11D with variable resistors VR3 and VR3'. Two variable resistors VR3 and VR3' are therefore necessary.

If only the variable resistor VR3 of the first output stage 11C same as Fig. 4 is used in the parallel push-pull structure using the first and second semiconductor devices 20 and 30 shown in Fig. 1, different bias voltages are applied to the first and second output stages 11C and 11D and an excessive load is applied to one of the first and second semiconductor devices 20 and 30 because of the following reasons. Referring to Fig. 6 in which the variable resistor VR3' shown in Fig. 5 is not used, the following relationship stands:

  • for the first output stage 11C V 0 = V 1 + 2 R ( i b 1 + i 2 ) and
  • for the second output stage 11D V 0 = V 2 + 2 R i b 2
where V0 is an output voltage of the bias circuit 50, i1 is a current flowing through the resistor R70, V1 is a bias voltage of the bias circuit 50, ib1 is a base current of the transistor Tr1 of the first output stage 11C, V2 is a voltage between the bases of the second output stage 11D, and R70 = R80 = R71 = R81 = R.

From the equations (2) and (3), it stands: V 1 + 2 R ( i b 1 + i 2 ) = V 2 + 2 R i b 2

Assuming that ib1 = ib2 = ib, then: V 1 + 2 R i b + 2 R i 2 = V 2 + 2 R i b

Therefore: V 1 + 2 R i 2 = V 2

As above, different bias voltages are applied to the first and second output stages 11C and 11D.

Consider now the B-class operation of the output stage shown in Fig. 1. In this case, even if the polarity of an input signal from the driver stage 10 changes, for example, from plus to minus, the transistor Tr2 is not cut off immediately and a through current (broken line I in Fig. 1) flows with some delay from the transistor Tr2 to the transistor Tr4 of the second semiconductor device 30 via the emitter resistors R2 and R4, because it takes a finite time for carriers accumulated in the base of the transistor Tr2 of the first semiconductor device 20 to be discharged. If this through current is large, the transistors Tr2 and Tr4 may be broken at the worst.

In the first and second semiconductor devices 20 and 30 show in Fig. 1, the emitter resistor R1 of the transistor Tr1 of the NPN power transistor 21 is connected between the emitter of the transistor Tr1 and the emitter of the transistor Tr2, and the emitter resistor R3 of the transistor Tr3 of the PNP power transistor 31 is connected between the emitter of the transistor Tr3 and the emitter of the transistor Tr4. Therefore, the discharge path of carriers accumulated in the base of the transistor Tr2 is from the base of the transistor Tr2, resistor R1, resistor R2, resistor R4, resistor R3, and to the emitter of the transistor Tr3. As the through current I starts flowing, the reverse voltage is generated across the resistors R2 and R4 so that carriers accumulated in the base of the transistor Tr2 become difficult to be discharged (reverse voltage across the resistor R2 is 235 V when the through current I is 5 A).

Therefore, in the circuit shown in Fig. 1, cutting the transistor Tr2 off is delayed. A relatively large through current I may flow in the high frequency band, for example, 10 kHz or higher, or crossover distortion may be generated because of a delay in cutting the transistor Tr2 off.

In contrast, in the circuit shown in Fig. 3, the emitter resistor R1' of the transistor Tr1 is connected to the second emitter terminal (E) and the emitter resistor R3' of the transistor Tr3 is connected to the second emitter terminal (E'). Therefore, if the polarity of an input signal changed from plus to minus for example, the discharge path of carriers accumulated in the base of the transistor Tr2 is from the base of the transistor Tr2, resistor R1', resistor R3', and to the emitter of the transistor Tr3 (refer to a broken line i in Fig. 3). Therefore, a reverse voltage generated across the resistors R2 and R4 by the through current I is applied to the resistors R1' and R3' to promote discharge and the transistor Tr2 is cut off rapidly. As a result, crossover distortion is hard to be generated. Furthermore, since a large through current I is prevented from flowing from the transistor Tr2 to the transistor Tr4, it is possible to avoid breakage of these transistors Tr2 and Tr4.

In the circuit shown in Fig. 3, the emitter resistors R2 and R4 of the transistors Tr2 and Tr4 are built in the first and second semiconductor devices 200 and 300. Another structure shown in Figs. 7A and 7B may be used. Namely, in first and second semiconductor devices 201 and 301, emitter resistors R2 and R4 are omitted. The emitter of the transistor Tr2 is connected to the first emitter terminal (E1), and the emitter of the transistor Tr4 is connected to the first emitter terminal (E1'). The emitter resistor of the transistor Tr2 having a desired value may be externally connected between the first emitter terminal (E1) and the second emitter terminal (E2), whereas the emitter resistor of the transistor Tr4 having a desired value may be externally connected between the first emitter terminal (E1') and the second emitter terminal (E2,).

In the circuit shown in Fig. 3, the NPN and PNP power transistors 21 and 31 of the first and second semiconductor devices 200 and 300 are each constituted of two-stage Darlington connected transistors. A three-stage or higher stage structure may also be used. For example, as in the case of first and second semiconductor devices 202 and 203 shown in Figs. 8A and 8B, an NPN power transistor 210 is constituted of three-stage Darlington connected transistors Tr20 to Tr22, and a PNP power transistor 310 is constituted of three-stage Darlington connected transistors Tr23 to Tr25. In this case, the emitters of the transistors Tr20 to Tr22 are connected via respective emitter resistors R20 to R22 to the second emitter terminal (E2), and the emitter of the final stage transistor Tr22 may be connected to the first emitter terminal (E1) to externally connect an additional emitter resistor to change the resistance value of the emitter resistor R22. Similarly, the emitters of the transistors Tr23 to Tr25 are connected via respective emitter resistors R23 to R25 to the second emitter terminal (E2'), and the emitter of the final stage transistor Tr25 may be connected to the first emitter terminal (E1.) to externally connect an additional emitter resistor to change the resistance value of the emitter resistor R25.

In the circuits shown in Figs. 8A and 8B, if E is the total forward voltage drop between the bases and emitters of the NPN and PNP power transistors 210 and 310 and A is the temperature coefficient of E, then E = 3.6V and A = 3 (&agr;1 + &agr;3). If B is the temperature coefficient of the forward voltage drop of the diodes 321 to 32n of the second semiconductor device 302, then B ≈ (A - &agr;2), i.e., &agr; 41 + &agr; 42 + + &agr; 4 n 3 ( &agr; 1 + &agr; 3 ) &agr; 2

For example, if the forward voltage drops VG1 to VGn of the diodes 321 to 32n are all the same and the temperature coefficients &agr;41 to &agr;4n of VG1 to VGn are all the same, then in the range of 0.1 V ≤ VGi ≤ 0.5 V V G i 2.6 / n &agr; 4 i ( 2 &agr; 1 + 2 &agr; 3 &agr; 2 ) / n where i = 1 - n If n = 5 and &agr;1 = &agr;3 = &agr;2, then VG1 = 2.6/5V and &agr;41 ≈ &agr;1.

In the circuits shown in Figs. 8A and 8B, the emitter resistors R22 and R25 of the transistors Tr2 and Tr4 are built in the first and second semiconductor devices 202 and 302. Another structure shown in Figs. 9A and 9B may be used. Namely, in first and second semiconductor devices 203 and 303, emitter resistors R22 and R25 are omitted. The emitter of the transistor Tr22 is connected to the first emitter terminal (E1), and the emitter of the transistor Tr25 is connected to the first emitter terminal (E1'). The emitter resistor of the transistor Tr22 having a desired value may be externally connected between the first emitter terminal (E1) and the second emitter terminal (E2), whereas the emitter resistor of the transistor Tr25 having a desired value may be externally connected between the first emitter terminal (E1') and the second emitter terminal (E2,).

In the circuits shown in Fig. 3, Figs. 7A to 9B, the base resistors R7' and R8' may be omitted.

Fig. 10 is a circuit diagram showing the structure of a driver stage and an output stage of a power amplifier according to the second embodiment of the invention. In Fig. 10, like constituent elements to those shown in Fig. 1 are represented by identical reference symbols.

A first semiconductor device 60 has a structure that the diode 22 and bias terminal (b) of the first semiconductor device 20 shown in Fig. 1 are removed. A second semiconductor device 70 has an NPN transistor Tr7 of the bias circuit formed on the same semiconductor substrate as the PNP power transistor 31, in place of the diodes 321 to 32n of the second semiconductor device 30 shown in Fig. 1. The emitter of the transistor Tr7 is connected to the base (base of transistor Tr3) of the PNP power transistor 31 and to the external connection base terminal (B'), and the base and collector of the transistor Tr7 are connected to external connection bias terminals (b1') and (b2'), respectively.

The forward voltage drop VBE between the base and emitter of the bias transistor Tr7 is about 0.6 V, and its temperature coefficient &agr;5 mV/°C takes a negative value, and &agr;5 ≈ &agr;1.

As shown in Fig. 11, when the first and second semiconductor devices 60 and 70 are juxtaposed side by side, the terminals (B), (C), (E1), and (E2) of the first semiconductor device 60 are symmetrical to the terminals (B'), (b1'), (b2'), (C'), (E1'), and (E2') of the second semiconductor device 70. Similar to the first embodiment, the printed patterns on the printed circuit board necessary for interconnections of the first or second emitter terminals, and collector terminals are made short.

The first and second semiconductor devices 60 and 70 having the matched electrical characteristics are SEPP connected and assembled in the manner same as the first embodiment except the bias circuit. The bias terminal (b1') of the second semiconductor device 70 is connected to the base terminal (B) of the first semiconductor device 60. Of an external resistor R9 and an external variable resistor VR4 serially connected and constituting a voltage divider circuit, one end of the resistor R9 or one end of the voltage divider circuit is connected to the bias terminal (b1'), the voltage dividing point is connected to the bias terminal (b2'), and one end of the variable resistor VR4 or the other end of the voltage divider circuit is connected to the base terminal (B'). The resistor R9, variable resistor VR4. and transistor Tr7 constitute a bias circuit 80.

The other structures are quite the same as Fig. 1.

For the transistor type bias circuit 80, the variable resistor VR4 is adjusted to set the vias voltage Vbias to about E. In practice, the variable resistor VR4 is adjusted so that the idling current takes a predetermined value at a predetermined high temperature.

According to the second embodiment, since it is easy to integrally form transistors on a semiconductor substrate, the component cost hardly rises. As the first and second semiconductor devices 60 and 70 are mounted on the heat sink, the transistor of the bias circuit for generating a proper bias voltage can be automatically mounted and the assembly works of the SEPP circuit can be simplified.

Since the bias transistor is formed on the same semiconductor substrate of the PNP power transistor of the second semiconductor device 70, ideal thermal coupling can be realized and good temperature compensation can be performed. If a combination of the complementary first and second semiconductor devices 60 and 70 is selected, the bias circuit transistor is automatically selected so that design of the SEPP circuit is simple.

Each of the first and second semiconductor devices 60 and 70 may be used as a conventional NPN or PNP power transistor.

The connection terminals are disposed so that when the first and second semiconductor devices 60 and 70 are juxtaposed side by side, first emitter terminals (E1) and (E1') and second emitter terminals (E2) and (E2') are positioned at the most inner side, and the collector terminals (C) and (C') are positioned at the second most inner side. Therefore, the printed patterns of the printed circuit board for the emitter and collector terminals necessary for the SEPP connection can be made short so that electromagnetic radiation is reduced and output distortion can be suppressed.

Since the emitter resistors R2 and R4 of the NPN and PNP power transistors are built in the first and second semiconductor devices 60 and 70, works and spaces for mounting the emitter resistors on the printed circuit board can be omitted.

One ends of the built-in emitter resistors R2 and R4 are connected to the second emitter terminals (E2) and (E2') different from the first emitter terminals (E1) and (E1'). Therefore, the emitter of the power transistor can be connected directly to an external circuit without being intervened by the built-in emitter resistor. In this case, the collector current of the power transistor can be monitored by measuring a voltage across the built-in emitter resistor, or another emitter resistor may be connected externally for changing the value of the built-in emitter resistor. The second emitter terminals (E2) and (E2') are positioned at the most inner side when the first and second semiconductor devices 60 and 70 are juxtaposed side by side. Therefore, in the standard case using the built-in emitter resistors, the second emitter terminals (E2) and (E2') can be interconnected by a shortest distance on the printed circuit board so that the length of the printed pattern for the loudspeaker output can be made shortest.

In the second embodiment, the fixed resistor R9 and variable resistor VR4 are connected externally. Instead, if a variation of the electrical characteristics of the first and second semiconductor devices is small, the fixed resistor R9 for generating an optimum vias voltage may be formed in the second semiconductor device and connected to the bias transistor. In this manner, the bias voltage adjustment can be ultimately dispensed with and the adjustment work of the bias circuit after the assembly of the SEPP circuit becomes unnecessary.

Since the number of interconnections for the bias circuit on the printed circuit board can be reduced, the mount area reduces. Therefore, the printed patterns of for the emitter and collector terminals to be formed on the printed circuit board for the SEPP connection can be shortened so that electromagnetic radiation is reduced and the generation of output distortion can be suppressed.

The bias transistor may use a PNP transistor and may be formed in the first semiconductor device.

The conditions of &agr;5 ≈ &agr;1, are not necessary to be strictly satisfied, but if both the values are not so much different, the temperature compensation near ideal state is possible.

Fig. 12 is a circuit diagram showing the structure of a driver stage and an output stage of a power amplifier according to a modification of the circuit shown in Fig. 10. In Fig. 12, like constituent elements to those shown in Fig. 10 are represented by identical reference symbols.

In the embodiment shown in Fig. 10, the oscillation suppressing resistors R7 and R8 are connected between the final stage transistors Tr5 and Tr6 of the driver stage 10 and the bias circuit 80. In this modification shown in Fig. 12, an oscillation suppressing base resistor R7' is connected between the base terminal (B) and the base of the transistor Tr1 of a first semiconductor device 600, and an oscillation suppressing base resistor R8' is connected between the base terminal (B') and the base of the transistor Tr3 of a second semiconductor device 700. The values of the base resistors R7' and R8' are about several &OHgr; to several hundreds &OHgr;, for example, 47 &OHgr;.

In the embodiment shown in Fig. 10, the emitter resistor R1 of the transistor Tr1 of the NPN power transistor 21 is connected between the emitters of the transistors Tr1 and Tr2, and the emitter resistor R3 of the transistor Tr3 of the PNP power transistor 31 is connected between the emitters of the transistors Tr3 and Tr4. In the modification shown in Fig. 12, the emitter resistor R1' of the transistor Tr1 is connected between the emitter of the transistor Tr1 and the second emitter terminal (E2), and the emitter resistor R3' of the transistor Tr3 is connected between the emitter of the transistor Tr3 and the second emitter terminal (E2'). The values of the resistors R1' and R3' are about 100 to 200 &OHgr;, for example 150 &OHgr;.

The other structures are the same as Fig. 10. The layout of the connection terminals of the first and second semiconductor devices 600 and 700 shown in Fig. 12 is the same as the first and second semiconductor devices 60 and 70 (refer to Fig. 11).

In the modification shown in Fig. 12, the oscillation suppressing resistors R7' and R8' are built in the first and second semiconductor devices 600 and 700. Therefore, by mounting the first and second semiconductor devices 600 and 700 on the heat sink, the oscillation suppressing resistors R7' and R8' are automatically assembled and it is not necessary to externally connect expensive inflammable resistors for oscillation suppression. Works and spaces for externally connecting such resistors on the printed circuit board can be dispensed with and the cost can be lowered.

Since the bias current will not flow through the resistors R7' and R8', the amount of current reduces and the voltage loss at the resistors R7' and R8' lowers. An output of the power amplifier can therefore be increased.

In the circuit shown in Fig. 12, the emitter resistor R1' of the transistor Tr1 is connected to the second emitter terminal (E) and the emitter resistor R3' of the transistor Tr3 is connected to the second emitter terminal (E'). Therefore, if the polarity of an input signal changed from plus to minus for example, the discharge path of carriers accumulated in the base of the transistor Tr2 is from the base of the transistor Tr2, resistor R1', resistor R3', and to the emitter of the transistor Tr3. Therefore, a reverse voltage generated across the resistors R2 and R4 by the through current is applied to the resistors R1' and R3' to promote discharge and the transistor Tr2 is cut off rapidly. As a result, crossover distortion is hard to be generated. Furthermore, since a large through current is prevented from flowing from the transistor Tr2 to the transistor Tr4, it is possible to avoid breakage of these transistors Tr2 and Tr4.

In configuring the parallel push-pull circuit similar to Fig. 4 by using two pairs of the first and second semiconductor devices 60 and 70 shown in Fig. 12, one voltage divider circuit of the bias circuit is used only by one of the two SEPP circuits because the oscillation suppressing base resistors R7' and R8' are built in the first and second semiconductor devices 600 and 700.

In the circuit shown in Fig. 12, the emitter resistors R2 and R4 built in the first and second semiconductor devices 600 and 700 may be omitted. In this case, the emitter of the transistor Tr2 is connected to the first emitter terminal (E1) and the emitter of the transistor Tr4 is connected to the first emitter terminal (E1').

The NPN and PNP power transistors 21 and 31 may be replaced by Darlington connected transistors of a three-stage or higher stage structure. In this case, the emitters of the Darlington connected transistors may be connected via respective emitter resistors to the second emitter terminals (E2) and (E2'), or the emitters other than the final stage may be connected via respective emitter resistors to the second emitter terminals (E2) and (E2') and the emitters of the last stage transistors are connected directly to the first emitter terminals (E1) and (E1').

According to the present invention, The total forward voltage drop V1 of the bias circuit diode or diodes of one of the first and second semiconductor devices is set to an arbitrary constant value smaller than E exclusive of about E/2, where E is a total forward voltage drop between the bases and emitters of the NPN and PNP power transistors of the first and second semiconductor devices. It is therefore possible to form an ordinary diode such as a PN junction diode on the same semiconductor substrate as the NPN or PNP power transistor. The manufacture is therefore easy and cost effective. The bias circuit diode of the other of the first and second semiconductor devices uses a Schottky barrier diode. Therefore, the forward voltage drop per one diode can be set finely in the range from 0.1 to 0.5 V, by using relatively simple structure. The total forward voltage drop V2 of the diodes can be easily set to a predetermined value of about (E - V1). As a result, only by mounting the first and second semiconductor devices on a heat sink, the diodes of a bias circuit for generating a proper bias voltage can be automatically mounted and the assembly work of the SEPP circuit can be simplified. Since Schottky diodes are used only for one of the first and second semiconductor devices, a rise of component cost is small.

The diodes of the first and second semiconductor devices are formed on the same semiconductor substrate as the NPN or PNP power transistor. Accordingly, ideal thermal coupling can be realized and good temperature compensation can be performed.

If a combination of the complementary first and second semiconductor devices is selected, the bias circuit diodes are automatically selected so that design of the SEPP circuit is simple.

Each of the first and second semiconductor devices may be used as a conventional NPN or PNP power transistor.

The bias circuit transistor for SEPP connection is formed on the semiconductor substrate same as the NPN or PNP power transistor of the first or second semiconductor device. Therefore, as the first and second semiconductor devices are mounted on a heat sink, the transistor of the bias circuit for generating a proper bias voltage can be automatically mounted and the assembly works of the SEPP circuit can be simplified.

Since the bias transistor is formed on the same semiconductor substrate as the NPN or PNP power transistor of the first or second semiconductor device, ideal thermal coupling can be realized and good temperature compensation can be performed.

If a combination of the complementary first and second semiconductor devices is selected, the bias circuit transistor is automatically selected so that design of the SEPP circuit is simple.

Transistors can be formed on a semiconductor substrate very easily so that the component cost hardly rises.

Each of the first and second semiconductor devices may be used as a conventional NPN or PNP power transistor.


Anspruch[de]
Halbleitereinrichtung mit: einer ersten Halbleitereinrichtung (20, 20A, 20B, 200, 200A, 200B, 201, 202 oder 203) mit einem auf einem ersten Halbleitersubstrat gebildeten NPN-Leistungstransistor (21 oder 210); und einer zweiten Halbleitereinrichtung (30, 30A, 30B, 300, 300A, 300B, 301, 302 oder 303) mit einem zu dem NPN-Leistungstransistor komplementären, auf einem zweiten Halbleitersubstrat gebildeten PNP-Leistungstransistor (31 oder 310), wobei die erste und die zweite Halbleitereinrichtung SEPP-verschaltet werden können, die erste Halbleitereinrichtung eine oder eine Mehrzahl seriell verschaltete, auf der ersten Halbleitereinrichtung gebildete Vorspannungsschaltungsdioden (22) aufweist, die Anodenseite der Diode oder der Dioden mit der Basis des NPN-Leistungstransistors und ihre Kathodenseite mit einem ersten Vorspannungsanschluss (b) verbunden ist, die zweite Halbleitereinrichtung eine oder eine Mehrzahl seriell verschaltete, auf der zweiten Halbleitereinrichtung gebildete Vorspannungsdioden (321, ..., 32n) aufweist und die Kathodenseite der Diode oder der Dioden mit der Basis des PNP-Leistungstransistors und ihre Anodenseite mit einem zweiten Vorspannungsanschluss (b') verbunden ist, wobei: der Gesamtvorwärtsspannungsabfall V1 der Vorspannungsschaltungsdiode oder - dioden entweder der ersten oder der zweiten Halbleitereinrichtung auf einen beliebigen konstanten Wert eingestellt ist, der kleiner als E ausschließlich etwa E/2 ist; und die Vorspannungsschaltungsdiode oder -dioden der anderen der ersten und der zweiten Halbleitereinrichtung Schottky-Barrierendioden sind und der Gesamtvorwärtsspannungsabfall V2 der Vorspannungsdiode oder -dioden auf einen vorbestimmten Wert von etwa (E-V1) eingestellt ist, wobei E ein Gesamtvorwärtsspannungsabfall zwischen den Basen und Emittern des NPN- und des PNP-Leistungstransistors der ersten und der zweiten Halbleitereinrichtung ist. Halbleitereinrichtung nach Anspruch 1, bei der ein Vorspannungseinstellwiderstand (VR3) seriell mit der/den Vorspannungsschaltungsdiode(n) der ersten oder der zweiten Halbleitereinrichtung verbunden ist. Halbleitereinrichtung nach Anspruch 1 oder 2, bei der: die erste Halbleitereinrichtung aufweist einen Basisanschluss (B), einen Kollektoranschluss (C) und einen Emitteranschluss (E1 oder E2), die jeweils verbunden sind mit der Basis-, der Kollektor- bzw. der Emitterseite des NPN-Leistungstransistors; und die zweite Halbleitereinrichtung aufweist einen Basisanschluss (B'), einen Kollektoranschluss (C') und einen Emitteranschluss (E1' oder E2'), die jeweils verbunden sind mit der Basis-, der Kollektor- bzw. der Emitterseite des PNP-Leistungstransistors, und wobei die Anschlüsse so angeordnet sind, dass bei Seite-an-Seite-Anordnung (Juxtaposition) der ersten und der zweiten Halbleitereinrichtung die Emitteranschlüsse an der innersten Seite und die Kollektoranschlüsse an der zweitinnersten Seite angeordnet sind. Halbleitereinrichtung nach Anspruch 3, bei der: ein Emitterwiderstand (R1, R1', R2, R20, R21 oder R22) geschaltet ist zwischen den Emitteranschluss und den Emitter des NPN-Leistungstransistors der ersten Halbleitereinrichtung; und ein Emitterwiderstand (R3, R3', R4, R23, R24 oder R25) geschaltet ist zwischen den Emitteranschluss und den Emitter des PNP-Leistungstransistors der zweiten Halbleitereinrichtung. Halbleitereinrichtung nach Anspruch 1, bei der: ein Emitterwiderstand (R1', R2, R20, R21 oder R22) an einem Ende verbunden ist mit dem Emitter des NPN-Leistungstransistors der ersten Halbleitereinrichtung, wobei sein anderes Ende verbunden ist mit einem zweiten Emitteranschluss (E2); und ein Emitterwiderstand (R3', R4, R23, R24 oder R25) an einem Ende verbunden ist mit dem Emitter des PNP-Leistungstransistors der zweiten Halbleitereinrichtung, wobei sein anderes Ende mit einem zweiten Emitteranschluss (E2') verbunden ist, wobei bei Seite-an-Seite-Anordnung (Juxtaposition) der ersten und der zweiten Halbleitereinrichtung die zweiten Emitteranschlüsse weiter innen angeordnet sind als Emitteranschlüsse. Halbleitereinrichtung nach Anspruch 1 oder 2, bei der: die Anodenseite der Vorspannungsschaltungsdiode (22) oder -dioden der ersten Halbleitereinrichtung verbunden ist mit einem Basisanschluss (B), wobei zwischen der Anodenseite und der Basis des NPN-Leistungstransistors ein Basiswiderstand (R7') verschaltet ist; und die Kathodenseite der Vorspannungsschaltungsdiode oder -dioden (321, ..., 32n) der zweiten Halbleitereinrichtung verbunden ist mit einem Basisanschluss (B'), wobei zwischen der Kathodenseite und der Basis des PNP-Leistungstransistors ein Basiswiderstand (R8') verschaltet ist. Halbleitereinrichtung nach Anspruch 6, bei der: die erste Halbleitereinrichtung einen Kollektoranschluss (C) und einen Emitteranschluss (E1) aufweist, die jeweils verbunden sind mit der Kollektor- bzw. der Emitterseite des NPN-Leistungstransistors; und die zweite Halbleitereinrichtung einen Kollektoranschluss (C') und einen Emitteranschluss (E1') aufweist, die jeweils verbunden sind mit der Kollektor- bzw. der Emitterseite des PNP-Leistungstransistors, und wobei die Anschlüsse so angeordnet sind, dass bei Seite-an-Seite-Anordnung (Juxtaposition) der ersten und der zweiten Halbleitereinrichtung die Emitteranschlüsse an der innersten Seite und die Kollektoranschlüsse an der zweitinnersten Seite angeordnet sind. Halbleitereinrichtung nach Anspruch 7, bei der: ein Emitterwiderstand (R1', R2, R20, R21 oder R22) verschaltet ist zwischen dem Emitteranschluss und dem Emitter des NPN-Leistungstransistors der ersten Halbleitereinrichtung; und ein Emitterwiderstand (R3', R4, R23, R24 oder R25) verschaltet ist zwischen dem Emitteranschluss und dem Emitter des PNP-Leistungstransistors der zweiten Halbleitereinrichtung. Halbleitereinrichtung nach Anspruch 7, bei der: ein Emitterwiderstand (R2, R20, R21 oder R22) an einem Ende verbunden ist mit dem Emitter des NPN-Leistungstransistors der ersten Halbleitereinrichtung, wobei sein anderes Ende mit einem zweiten Emitteranschluss (E2) verbunden ist; und ein Emitterwiderstand (R4, R23, R24 oder R25) an einem Ende verbunden ist mit dem Emitter des PNP-Leistungstransistors der zweiten Halbleitereinrichtung, wobei sein anderes Ende mit einem zweiten Emitteranschluss (E2') verbunden ist, wobei bei Seite-an-Seite-Anordnung (Juxtaposition) der ersten und der zweiten Halbleitereinrichtung die zweiten Emitteranschlüsse weiter innen angeordnet sind als Emitteranschlüsse. Halbleitereinrichtung nach Anspruch 1 oder 2, bei der: der NPN-Leistungstransistor der ersten Halbleitereinrichtung Darlington-verschaltete n-Stufen-NPN-Transistoren (Tr1, Tr2) aufweist, wobei der Emitter jedes n-Stufen-NPN-Transistors über einen Emitterwiderstand (R1 oder R2) mit einem Emitteranschluss (E1 oder E2) verbunden ist; und die PNP-Leistungstransistoren der zweiten Halbleitereinrichtung Darlington-verschaltete n-Stufen-PNP-Transistoren (Tr3, Tr4) aufweisen, wobei der Emitter jedes n-Stufen-PNP-Transistors über einen Emitterwiderstand (R3 oder R4) mit einem Emitteranschluss (E1' oder E2') verbunden ist. Halbleitereinrichtung nach Anspruch 10, bei der: die erste Halbleitereinrichtung einen Basisanschluss (B) und einen Kollektoranschluss (C) aufweist, die jeweils verbunden sind mit der Basis- bzw. Kollektorseite des NPN-Leistungstransistors; und die zweite Halbleitereinrichtung einen Basisanschluss (B') und einen Kollektoranschluss (C') aufweist, die jeweils mit der Basis- bzw. der Kollektorseite des PNP-Leistungstransistors verbunden sind, und wobei die Anschlüsse so angeordnet sind, dass bei Seite-an-Seite-Anordnung (Juxtaposition) der ersten und der zweiten Halbleitereinrichtung die Emitteranschlüsse an der innersten Seite und die Kollektoranschlüsse an der zweitinnersten Seite angeordnet sind. Halbleitereinrichtung nach Anspruch 1 oder 2, bei der: der NPN-Leistungstransistor der ersten Halbleitereinrichtung Darlington-verschaltete n-Stufen-NPN-Transistoren (Tr20, Tr21, Tr22) aufweist, wobei der Emitter des NPN- . Transistors (Tr22) der letzten Stufe mit einem ersten Emitteranschluss (E1) verbunden ist und die Basis jedes der NPN-Transistoren der zweiten und folgenden Stufen über einen Emitterwiderstand (R21 oder R22) mit einem zweiten Emitteranschluss (E2) verbunden ist; und der PNP-Leistungstransistor (310) der zweiten Halbleitereinrichtung (302, 303) Darlington-verschaltete n-Stufen-PNP-Transistoren (Tr23, Tr24, Tr25) aufweist, wobei der Emitter des PNP-Transistors (Tr25) der letzten Stufe mit einem ersten Emitteranschluss (E1) verbunden ist und die Basis jedes der PNP-Transistoren (Tr24, Tr25) der zweiten und folgenden Stufen über einen Emitterwiderstand (R24 oder R25) mit einem zweiten Emitteranschluss (E2') verbunden ist. Halbleitereinrichtung nach Anspruch 12, bei der: die erste Halbleitereinrichtung einen Basisanschluss (B) und einen Kollektoranschluss (C) aufweist, die jeweils mit der Basis- bzw. der Kollektorseite des NPN-Leistungstransistors verbunden sind; und die zweite Halbleitereinrichtung einen Basisanschluss (B') und einen Kollektoranschluss (C') aufweist, die jeweils mit der Basis- bzw. der Kollektorseite des PNP-Leistungstransistors verbunden sind, und wobei die Anschlüsse so angeordnet sind, dass bei Seite-an-Seite-Anordnung (Juxtaposition) der ersten und der zweiten Halbleitereinrichtung die zweiten Emitteranschlüsse an der innersten Seite angeordnet sind, die ersten Emitteranschlüsse an der zweitinnersten Seite angeordnet sind, und die Kollektoranschlüsse an der drittinnersten Seite angeordnet sind.
Anspruch[en]
A semiconductor device comprising: a first semiconductor device (20, 20A, 20B, 200, 200A, 200B, 201, 202 or 203) having an NPN power transistor (21 or 210) formed on a first semiconductor substrate; and a second semiconductor device (30, 30A, 308, 300, 300A, 300B, 301, 302 or 303) having a PNP power transistor (31 or 310) complementary to the NPN power transistor formed on a second semiconductor substrate, said first and second semiconductor devices capable of being SEPP connected, said first semiconductor device having one or a plurality of serially connected bias circuit diodes (22) formed on the first semiconductor device, the anode side of the diode or diodes being connected to the base of the NPN power transistor and the cathode side thereof being connected to a first bias terminal (b), said second semiconductor device having one or a plurality of serially connected bias circuit diodes (321,..., 32n) formed on the second semiconductor device, the cathode side of the diode or diodes being connected to the base of the PNP power transistor and the anode side thereof being connected to a second bias terminal (b'), wherein: the total forward voltage drop V1 of the bias circuit diode or diodes of one of said first and second semiconductor devices is set to an arbitrary constant value smaller than E exclusive of about E/2; and the bias circuit diode or diodes of the other of said first and second semiconductor devices are Schottky barrier diodes and the total forward voltage drop V2 of the bias diode or diodes is set to a predetermined value of about (E - V1) where E is a total forward voltage drop between the bases and emitters of the NPN and PNP power transistors of said first and second semiconductor devices. A semiconductor device according to claim 1, wherein a bias voltage adjusting resistor (VR3) is serially connected to the bias circuit diode or diodes of said first or second semiconductor device. A semiconductor device according to claim 1 or 2, wherein: said first semiconductor device includes a base terminal (B), a collector terminal (C), and an emitter terminal (E1 or E2) respectively connected to the base, collector, and emitter sides of the NPN power transistor; and said second semiconductor device includes a base terminal (B'), a collector terminal (C'), and an emitter terminal (E1' or E2') respectively connected to the base, collector, and emitter sides of the PNP power transistor, and wherein the terminals are disposed so that when said first and second semiconductor devices are juxtaposed side by side, the emitter terminals are positioned at the most inner side and the collector terminals are positioned at the second most inner side. A semiconductor device according to claim 3, wherein: an emitter resistor (R1, R1', R2, R20, R21 or R22) is connected between the emitter terminal and the emitter of the NPN power transistor of said first semiconductor device; and an emitter resistor (R3, R3', R4, R23, R24 or R25) is connected between the emitter terminal and the emitter of the PNP power transistor of said second semiconductor device. A semiconductor device according to claim 1, wherein: an emitter resistor (R1', R2, R20, R21 or R22) is connected at one end to the emitter of the NPN power transistor of said first semiconductor device, the other end thereof being connected to a second emitter terminal (E2); and an emitter resistor (R3', R4, R23, R24 or R25) is connected at one end to the emitter of the PNP power transistor of said second semiconductor device, the other end thereof being connected to a second emitter terminal (E2'), wherein when said first and second semiconductor devices are juxtaposed side by side, the second emitter terminals are positioned more inner than emitter terminals. A semiconductor device according to claim 1 or 2, wherein: the anode side of the bias circuit diode (22) or diodes of said first semiconductor device is connected to a base terminal (B), a base resistor (R7') being connected between the anode side and the base of the NPN power transistor; and the cathode side of the bias circuit diode or diodes (321, ..., 32n) of said second semiconductor device is connected to a base terminal (B'), a base resistor (R8') being connected between the cathode side and the base of the PNP power transistor. A semiconductor device according to claim 6, wherein: said first semiconductor device includes a collector terminal (C) and an emitter terminal (E1) respectively connected to the collector and emitter sides of the NPN power transistor; and said second semiconductor device includes a collector terminal (C') and an emitter terminal (E1') respectively connected to the collector and emitter sides of the PNP power transistor, and wherein the terminals are disposed so that when said first and second semiconductor devices are juxtaposed side by side, the emitter terminals are positioned at the most inner side and the collector terminals are positioned at the second most inner side. A semiconductor device according to claim 7, wherein: an emitter resistor (R1', R2, R20, R21 or R22) is connected between the emitter terminal and the emitter of the NPN power transistor of said first semiconductor device; and an emitter resistor (R3', R4, R23, R24 or R25) is connected between the emitter terminal and the emitter of the PNP power transistor of said second semiconductor device. A semiconductor device according to claim 7, wherein: an emitter resistor (R2, R20, R21 or R22) is connected at one end to the emitter of the NPN power transistor of said first semiconductor device, the other end thereof being connected to a second emitter terminal (E2); and an emitter resistor (R4, R23, R24 or R25) is connected at one end to the emitter of the PNP power transistor of said second semiconductor device, the other end thereof being connected to a second emitter terminal (E2'), wherein when said first and second semiconductor devices are juxtaposed side by side, the second emitter terminals are positioned more inner than emitter terminals. A semiconductor device according to claim 1 or 2, wherein: the NPN power transistor of said first semiconductor device includes Darlington connected n-stage NPN transistors (Tr1, Tr2), the emitter of each of n-stage NPN transistors being connected via an emitter resistor (R1 or R2) to an emitter terminal (E1 or E2); and the PNP power transistor of said second semiconductor device includes Darlington connected n-stage PNP transistors (Tr3, Tr4), the emitter of each of n-stage PNP transistors being connected via an emitter resistor (R3 or R4) to an emitter terminal (E1' or E2'). A semiconductor device according to claim 10, wherein: said first semiconductor device includes a base terminal (B) and a collector terminal (C) respectively connected to the base and collector sides of the NPN power transistor; and said second semiconductor device includes a base terminal (B') and a collector terminal (C') respectively connected to the base and collector sides of the PNP power transistor, and wherein the terminals are disposed so that when said first and second semiconductor devices are juxtaposed side by side, the emitter terminals are positioned at the most inner side and the collector terminals are positioned at the second most inner side. A semiconductor device according to claim 1 or 2, wherein: the NPN power transistor of said first semiconductor device includes Darlington connected n-stage NPN transistors (Tr20, Tr21, Tr22), the emitter of the last stage NPN transistor (Tr22) being connected to a first emitter terminal (E1) and the base of each of the second and following stage NPN transistors being connected via an emitter resistor (R21 or R22) to a second emitter terminal (E2); and the PNP power transistor (310) of said second semiconductor device (302, 303) includes Darlington connected n-stage PNP transistors (Tr23, Tr24, Tr25), the emitter of the last stage PNP transistor (Tr25) being connected to a first emitter terminal (E1) and the base of each of the second and following stage PNP transistors (Tr24, Tr25) being connected via an emitter resistor (R24 or R25) to a second emitter terminal (E2'). A semiconductor device according to claim 12, wherein: said first semiconductor device includes a base terminal (B) and a collector terminal (C) respectively connected to the base and collector sides of the NPN power transistor, and said second semiconductor device includes a base terminal (B') and a collector terminal (C') respectively connected to the base and collector sides of the PNP power transistor, and wherein the terminals are disposed so that when said first and second semiconductor devices are juxtaposed side by side, the second emitter terminals are positioned at the most inner side, the first emitter terminals are positioned at the second most inner side, and the collector terminals are positioned at the third most inner side.
Anspruch[fr]
Un dispositif semi-conducteur comprenant: un premier dispositif semi-conducteur (20, 20A, 20B, 200, 200A, 200B, 201, 202 ou 203) comprenant un transistor de puissance NPN (21 ou 210) formé sur un premier substrat semi conducteur; et un second dispositif semi-conducteur (30, 30A, 30B, 300, 300A, 300B, 301, 302 ou 303) comprenant un premier transistor de puissance PNP (31 ou 310) complémentaire au transistor de puissance NPN formé sur un second substrat semi conducteur; lesdits premier et second dispositifs semi-conducteurs étant capables d'être connectés en push-pull à sortie unique, ledit dispositif semi conducteur comprenant une ou une pluralité de diodes de circuit de polarisation connectées en série (22) formées sur le premier dispositif semi-conducteur, le côté anode de la ou des diodes étant connecté à la base du transistor de puissance NPN et son côté cathode étant connecté à une première borne de polarisation (b), ledit second dispositif semi-conducteur comprenant une ou une pluralité de diodes de circuit de polarisation connectées en série (321, ..., 32n) formées sur le second dispositif semi-conducteur, le côté cathode de la ou des diodes étant connecté à la base ou transistor de puissance PNP et son côté anode étant connecté à une seconde borne de polarisation (b'), où: la chute de tension totale V1 dans le sens direct de la ou des diodes de circuit de polarisation d'un desdits premier et second dispositifs semi conducteurs est réglée à une valeur constante arbitraire plus petite que E en excluant environ E/2; et la ou les diodes de circuit de polarisation de l'autre desdits premier et second dispositifs semi-conducteurs sont des diodes à barrière de Schottky, et la chute de tension totale V2 dans le sens direct de la ou des diodes de polarisation est réglée à une valeur prédéterminée d'environ (E - V1) où E est la chute de tension totale dans le sens direct entre les bases et les émetteurs des transistors de puissance NPN et PNP desdits premier et second dispositifs semi-conducteurs, Un dispositif semi-conducteur selon la revendication 1, dans lequel une résistance de réglage de tension de polarisation (VR3) est connectée en série à la ou aux diodes de circuit de polarisation dudit premier ou second dispositif semi-conducteur. Un dispositif semi-conducteur selon la revendication 1 ou 2, dans lequel

ledit premier dispositif semi-conducteur comprend une borne de base (B), une borne de connecteur (C) et une borne d'émetteur (E1 ou E2) connectées respectivement aux côtés de base, de collecteur et d'émetteur du transistor de puissance NPN; et

ledit second dispositif semi-conducteur comprend une borne de base (B'), une borne de collecteur (C') et une borne d'émetteur (E1' ou E2') respectivement connectées aux côtés de base, de collecteur et d'émetteur du transistor de puissance PNP, et où

les bornes sont disposées de telle manière que, lorsque lesdits premier et second dispositifs semi-conducteurs sont juxtaposés côte à côte, les bornes d'émetteur sont positionnées au niveau du côté le plus interne et les bornes de collecteur sont positionnées aux niveau du second côté plus interne.
Un dispositif semi-conducteur selon la revendication 3, dans lequel: une résistance d'émetteur (R1, R1', R2, R20, R21 ou R22) est connectée entre la borne d'émetteur et l'émetteur du transistor de puissance NPN dudit premier dispositif semi-conducteur; et une résistance d'émetteur (R3, R3', R4, R23, R24 ou R25) est connectée entre la borne d'émetteur et l'émetteur de transistor de puissance PNP dudit second dispositif semi-conducteur. un dispositif semi-conducteur selon la revendication 1, dans lequel: une résistance d'émetteur (R1', R2, R20, R21 ou R22) est connectée par une extrémité à l'émetteur du transistor de puissance NPN dudit premier dispositif semi-conducteur, son autre extrémité étant connectée à une seconde borne d'émetteur (E2); et une résistance d'émetteur (R3', R4, R23, R24, R25) est connectée par une extrémité à l'émetteur de transistor de puissance PNP dudit second dispositif semi-conducteur, son autre extrémité étant connectée à une seconde borne d'émetteur (E2'), où lorsque lesdits premier et second dispositifs semi-conducteurs sont juxtaposés côte à côte, les secondes bornes d'émetteur sont positionnées davantage à l'intérieur que les bornes d'émetteur. Un dispositif semi-conducteur de la revendication 1 ou 2, dans lequel: le côté anode de la (22) ou des diodes de circuit de polarisation dudit premier dispositif seul conducteur est connecté à une borne de base (B), une résistance de base (R7') étant connectée entre le côté anode et la base du transistor de puissance NPN; et le côté cathode de la ou des diodes de circuit de polarisation (321, ..., 32n) dudit second dispositif semi-conducteur est connecté à une borne de base (B'), une résistance de base (R8') étant connectée entre le côté cathode et la base du transistor de puissance PNP. Un dispositif semi-conducteur selon la revendication 6, dans lequel: ledit premier dispositif semi-conducteur comprend une borne de collecteur (C) et une borne d'émetteur (E1) connectées respectivement aux côtés de collecteur et d'émetteur du transistor de puissance NPN; et ledit second dispositif semi-conducteur comprend une borne de collecteur (C') et une borne d'émetteur (E1') connectées respectivement aux côtés de collecteur et d'émetteur du transistor de puissance PNP, et où les bornes sont disposées de telle manière que, lorsque lesdits premier et second dispositifs semi-conducteurs sont juxtaposés côte à côte, les bornes d'émetteur sont positionnés au niveau du côté le plus interne et les bornes de collecteur sont positionnés au niveau du second côté le plus interne. Un dispositif semi-conducteur selon la revendication 7, dans lequel: une résistance d'émetteur (R1, R2, R20, R21 ou R22) est connectée entre la borne d'émetteur et l'émetteur du transistor de puissance NPN dudit premier dispositif semi-conducteur; et une résistance d'émetteur (R3', R4, R23, R24 ou R25) est connectée entre la borne d'émetteur et l'émetteur du transistor de puissance PNP dudit second dispositif semi-conducteur. Un dispositif semi-conducteur selon la revendication 7, dans lequel: une résistance d'émetteur (R2, R20, R21 ou R22) est connectée par une extrémité à l'émetteur du transistor de puissance NPN dudit premier dispositif semi-conducteur, son autre extrémité étant connectée à une seconde borne d'émetteur (E2); et une résistance d'émetteur (R4, R23, R24 ou R25) est connectée par une extrémité à l'émetteur du transistor de puissance PNP dudit second dispositif semi-conducteur, son autre extrémité étant connectée à une seconde borne d'émetteur (E2'), où lorsque lesdits premier et second dispositifs semi-conducteurs sont juxtaposés côte à côte, les secondes bornes d'émetteur sont positionnées davantage à l'intérieur que des bornes d'émetteur. Un dispositif semi-conducteur selon la revendication 1 ou 2, dans lequel: le transistor de puissance NPN dudit second dispositif semi-conducteur comprend des transistors NPN à n étages connectés en Darlington (Tr1, Tr2), l'émetteur de chacun des transistors NPN à n étages étant connecté, par l'intermédiaire d'une résistance d'émetteur (R1 ou R2), à une borne d'émetteur (E1 ou E2); et le transistor de puissance PNP dudit second dispositif semi-conducteur comprend des transistors PNP n étages connectés en Darlington (Tr3, Tr4), l'émetteur de chacun des transistors PNP à n étages étant connecté, par l'intermédiaire d'une résistance d'émetteur (R3 ou R4 ), à une borne d'émetteur (E1' ou E2'). Un dispositif semi-conducteur selon la revendication 10, dans lequel: ledit premier dispositif semi-conducteur comprend une borne de base (B) et une borne de collecteur (C) respectivement connectées aux côtés de base et de collecteur du transistor de puissance NPN; et ledit second dispositif semi-conducteur comprend une borne de base (B') et une borne de collecteur (C') respectivement connectées aux côtés de base et de collecteur du transistor de puissance NPN, et où les bornes sont disposées de telle manière que, lorsque lesdits premier et second dispositifs semi-conducteurs sont juxtaposés côte à côte, les bornes d'émetteur sont positionnées au niveau du côté le plus interne et les bornes de collecteur sont positionnées au niveau du second côté le plus interne. Un dispositif semi-conducteur selon la revendication 1 ou 2, dans lequel: le transistor de puissance NPN dudit premier dispositif semi-conducteur comprend des transistors NPN à n étage connectés en Darlington (Tr20, Tr21, Tr22), l'émetteur du transistor NPN du dernier étage (Tr22) étant connecté à une première borne d'émetteur (E1) et la base de chacun des transistor NPN de second étage et des étages suivants étant connectée, par l'intermédiaire d'une résistance d'émetteur (R21 ou R22), à une seconde borne d'émetteur (E2); et le transistor de puissance PNP (310) dudit second dispositif semi-conducteur (302, 303) comprend des transistors PNP à n étages connectés en Darlington (Tr23, Tr24, Tr25), l'émetteur du transistor PNP de dernier étage (Tr25) étant connecté à une première borne d'émetteur (E1) et la base de chacun des transistors PNP de second étage et des étages suivants (Tr24, Tr25) étant connectée, par l'intermédiaire d'une résistance d'émetteur (R24 ou R25), à une seconde borne d'émetteur (E2'). Un dispositif semi-conducteur selon la revendication 12, dans lequel: ledit premier dispositif semi-conducteur comprend une borne de base (B) et une borne de collecteur (C) respectivement connectées aux côtés de base et de collecteur du transistor de puissance NPN; et ledit second dispositif semi-conducteur comprend une borne de base (B') et une bande de collecteur (C') respectivement connectées aux côtés de base et de collecteur du transistor de puissance PNP, et où les bornes sont disposées de telle manière que, lorsque lesdits premier et second dispositifs semi-conducteur sont juxtaposés côte à côte, les seconds bornes d'émetteur sont positionnées au niveau du côté le plus interne, les premières bornes d'émetteur sont positionnées au niveau du second côté le plus interne, et les bornes de collecteur sont positionnées au niveau du troisième côté le plus interne.






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