PatentDe  


Dokumentenidentifikation EP1097415 29.06.2006
EP-Veröffentlichungsnummer 0001097415
Titel NIEDRIGE LEISTUNGSSPANNUNGSREFERENZ MIT VERBESSERTER VERSORGUNGSSPANNUNGSUNTERDRÜCKUNG
Anmelder Micrel Inc., San Jose, Calif., US
Erfinder YEE, W., Philip, Los Altos, CA 94022, US
Vertreter derzeit kein Vertreter bestellt
DE-Aktenzeichen 60028156
Vertragsstaaten DE, GB
Sprache des Dokument EN
EP-Anmeldetag 17.05.2000
EP-Aktenzeichen 009326687
WO-Anmeldetag 17.05.2000
PCT-Aktenzeichen PCT/US00/13949
WO-Veröffentlichungsnummer 0000072103
WO-Veröffentlichungsdatum 30.11.2000
EP-Offenlegungsdatum 09.05.2001
EP date of grant 24.05.2006
Veröffentlichungstag im Patentblatt 29.06.2006
IPC-Hauptklasse G05F 3/30(2006.01)A, F, I, 20051017, B, H, EP

Beschreibung[en]
1. Field Of The Invention

The invention generally relates to a voltage reference circuit and, in particular, the present invention relates to a voltage reference circuit with improved line regulation and having minimal operating voltage and current.

2. Background of the Invention

Figure 1 is a conventional bandgap voltage reference circuit 10 for providing a reference voltage that is relatively constant over a sufficiently large temperature range. Bandgap reference circuit 10 includes a first bipolar transistor Q1 and a second bipolar transistor Q2 having their base terminals connected together. A current mirror formed by PMOS transistors M1 and M2 causes a first current Ic1 which flows through transistor M1 to be mirrored as an identical second current Ic2 which flows through transistor M2. Appropriate start-up circuitry (not shown) is provided to ensure that circuit 10 does not remain in the unstable equilibrium point where currents Ic1 and Ic2 are equal to zero.

In bandgap reference circuit 10, the emitter area of Q1 is made to be n times the emitter area of Q2, causing different current densities to flow in the transistors since the current mirror forces the currents of transistors Q1 and Q2 to be equal. Typically, the transistor size ratio n is in the range of 2 to 10. The unequal current densities of transistors Q1 and Q2 imply that if their currents are to be equal as required by the operation of the current mirror, then the base to emitter voltages (VBE) of Q1 and Q2 must be different. The difference in the base to emitter voltages, denoted &Dgr;VBE, is developed across a resistor R1. The voltage &Dgr;VBE is given by the equation: &Dgr; V B E = k T q ln ( n )

where k is the Boltzmann's constant, T is temperature in Kelvin, and q is the electric charge. The same current that flows in resistor R1 also flows in resistor R2 and a voltage VR2 develops across resistor R2. Voltage VR2 is proportional to voltage &Dgr;VBE according to the equation: V R 2 = &Dgr; V B E ( R 2 R 1 )

where R1 and R2 represent the resistance of resistors R1 and R2.

The output voltage Vout at node 16 is the sum of the voltage VR2 and the voltage VBE of transistor Q2. It is well known that the voltage VBE of a bipolar transistor has a negative temperature coefficient while the voltage &Dgr;VBE has a positive voltage coefficient. By properly ratioing the resistance of resistors R1 and R2, a constant output voltage having approximately zero temperature coefficient can be obtained over a wide range of temperatures. For circuit 10 of Figure 1, a nominal output voltage of approximately 1.25 volts is realized at node 16.

It is desirable to provide a bandgap voltage reference circuit where the operating voltage and operating current of the reference circuit can be kept at minimal levels, i.e., the reference circuit must consume minimal power in operation. Voltage reference circuit 10 of Figure 1 achieves low power consumption by utilizing only two current paths from the power supply Vs (node 12) to the ground potential (node 14). By providing only two current paths, the supply current which flows in circuit 10 in operation is kept low. Voltage reference circuit 10 also allows the supply voltage Vs to be at a minimum by using PMOS transistors to implement the current mirror (i.e., transistors M1 and M2). PMOS transistor M2 requires only a minimal voltage between supply voltage Vs (node 12) and voltage Vout (node 16) for its operation as a current mirror. Furthermore, in reference voltage circuit 10, PMOS transistors M1 and M2 are long channel devices so as to maximize their output impedance.

However, conventional voltage reference circuits such as reference circuit 10 exhibit poor line regulation characteristics. Line regulation is defined as the dependence of the output voltage (Vout) on the power supply voltage (Vs). Reference voltage circuit 10 has poor line regulation characteristics due to the finite Early voltage value of transistor Q1. The Early voltage (VA) is an extrapolated voltage parameter modeling the variation of the collector current Ic with respect to the collector to emitter voltage VCE in a bipolar transistor. For a description of the Early voltage of a bipolar transistor and the Early effect on the transistor output characteristics, see Gray and Meyer, "Analysis and Design of Integrated Circuits," 2nd ed., 1984, John Wiley & Sons, Inc., pages 18-19.

Referring to Figure 1, as the supply voltage Vs (node 12) varies, voltage VCE of transistor Q1 is caused to vary accordingly. Because transistor Q1 has a finite Early voltage, the change in voltage VCE of transistor Q1 causes its collector current IC1 to also vary. Because current IC1 is mirrored to current IC2 of transistor Q2, current IC2 flowing through resistor R2 varies as a result of the variation in supply voltage Vs. Therefore, the output voltage Vout (node 16) of voltage reference circuit 10 varies with the supply voltage Vs. Even though voltage reference circuit 10 is capable of providing a constant output voltage over a wide range of temperature, the output voltage exhibits the undesirable characteristics of poor line regulation.

Prior art solutions to control the line regulation character are unsatisfactory because the solutions involve placing additional voltage or current burdens on the circuit, making it undesirable for minimal power operations.

Therefore, it is desirable to provide a voltage reference circuit with improved line regulation characteristics which can be operated with minimal operating voltage and current.

GB-A-2263794 discloses a reference voltage circuit employing bipolar transistors and generally corresponding to the preambles of claims 1 and 21.

SUMMARY OF THE INVENTION

In accordance with a first aspect of the present invention, there is provided a voltage reference circuit comprising:

  • a current mirror electrically coupled to a first supply voltage, said current mirror having a first current terminal and a second current terminal;
  • a first transistor (Q1) having a first current handling terminal, a second current handling terminal coupled to said first current terminal of said current mirror, and a control terminal;
  • a second transistor (Q2) having a first current handling terminal coupled to a second supply voltage, a second current handling terminal, and a control terminal coupled to said second current handling terminal, said control terminal also coupled to said control terminal of said first transistor;
  • a first resistor (R1) coupled between said first current handling terminal of said first transistor and said second supply voltage; and
  • a second resistor (R2) coupled between said second current terminal of said current mirror and said second current handling terminal of said second transistor, characterized in that
  • said first resistor has a variable resistance, said resistance being modulated by a first bias voltage related to said first supply voltage.

In accordance with a second aspect of the present invention, there is provided a voltage reference circuit comprising:

  • a current mirror electrically coupled to a first supply voltage, said current mirror having a first current terminal and a second current terminal;
  • a first transistor (Q1) having a first current handling terminal coupled to a second supply voltage, a second current handling terminal coupled to said first current terminal of said current mirror, and a control terminal;
  • a second transistor (Q2) having a first current handling terminal coupled to said second supply voltage, a second current handling terminal coupled to said control terminal of said first transistor, and a control terminal coupled to a first node;
  • a first resistor (R1) coupled between said second current handling terminal of said second transistor and said first node; and
  • a second resistor (R2) coupled between said first node and said second current terminal of said current mirror, characterized in that
  • said first resistor has a variable resistance, said resistance being modulated by a first bias voltage related to said first supply voltage.

In one embodiment of the present invention, a voltage reference circuit includes a first transistor and a second transistor having their control terminals connected together, a first resistor coupled to a first current handling terminal of the first transistor, a second resistor coupled between an output node and a second current handling terminal of the second transistor, and a current mirror. The reference circuit provides an output voltage at the output node that is virtually independent of variations in the supply voltage by dynamically adjusting the resistance of the first resistor in response to changes in the supply voltage. The voltage at the control terminals of the first and second transistors is thus kept constant despite variations in the supply voltage. A first current and a second current flowing through the first and second transistors, respectively, are also kept constant.

In another embodiment of the present invention, a voltage reference circuit includes a first transistor, a second transistor, a first resistor and a second resistor connected in series between an output node and a second current handling terminal of the second transistor, and a current mirror. A first current flowing through the first transistor is kept constant with variations in the supply voltage by adjusting the base to emittier VBE voltage of the first transistor. The voltage VBE is adjusted in an amount sufficient to offset any changes in the first current that would be caused by variations in the supply voltage if the voltage VBE remained constant. The voltage VBE is adjusted by varying the resistance of the first resistor. In yet another embodiment, the voltage VBE is adjusted by varying the resistance of both the first and second resistors.

The voltage reference circuit of the present invention provides a reference voltage at the output node that is temperature independent and supply voltage independent over a large range of temperature and supply voltages. Furthermore, the voltage reference circuit improves line regulation without adding voltage or current burdens on the circuit.

The present invention is better understood upon consideration of the detailed description below and the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

  • Figure 1 is a circuit schematic of a conventional voltage reference circuit.
  • Figure 2 is a circuit schematic of a voltage reference circuit according to a first embodiment of the present invention.
  • Figure 3 is a circuit schematic of a voltage reference circuit according to a third embodiment of the present invention.
  • Figure 4 is a circuit schematic of a voltage reference circuit according to a fourth embodiment of the present invention.
  • Figure 5 is a cross-sectional view of a diffusion resistor structure.

In the present disclosure, like objects which appear in more than one figure are provided with like reference numerals.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

A low power voltage reference circuit with improved line regulation characteristics is described. The voltage reference circuit of the present invention improves line regulation without placing any additional voltage or current demands on the circuit.

Figure 2 is a circuit schematic of a voltage reference circuit 20 according to a first embodiment of the present invention. Voltage reference circuit 20 includes a first transistor Q1 and a second transistor Q2. Transistors Q1 and Q2 are NPN bipolar transistors. In the present embodiment, the size of transistor Q1 is n times the size of transistor Q2. Typically, the size of a bipolar transistor is determined by its emitter area. Transistor Q2 is diode connected, i.e., its base and collector terminals are tied together. The base terminals of transistors Q1 and Q2 are also tied together. A resistor R1 including a pair of serially connected resistors R1a and R1b are connected between the emitter terminal of transistor Q1 and ground potential (node 24). Another resistor R2 is connected between the collector terminal of transistor Q2 and an output node 30 providing the reference output voltage Vout.

Voltage reference circuit 20 further includes a current mirror formed by PMOS transistors M1 and M2. Of course, other transistor types can be used, such as bipolar transistors. Transistor M1 is connected between a power supply voltage Vs (node 22) and the collector terminal of transistor Q1. Transistor M1 has its gate terminal and its drain terminal connected together. The gate terminals of transistors M1 and M2 are tied together. Transistor M2 is connected between the power supply voltage Vs (node 22) and output node 30.

In voltage reference circuit 20, resistors R1a, R1b and R2 are diffusion resistors. Diffusion resistors are well known in the art. Examples of diffused resistors are described in pages 113-118 of Gray and Meyer, "Analysis and Design of Integrated Circuits" 2nd ed., 1984, John Wiley & Sons, Inc., which is incorporated by reference in its entirety. The diffusion resistors of the present embodiment utilize a base-diffused resistor structure similar to that shown on page 114 of Gray and Meyer and in Figure 5. Figure 5 is a cross-sectional view of a diffusion resistor 82. Diffusion resistor 82 is fabricated on a p-type substrate 84 and is contained in an n-type epitaxial layer 88 including an n+ buried layer 86. Resistor 82 is defined by a p-type diffusion region 90. Resistor contacts 92 and 94 are formed at the two ends of p-type diffusion region 90 in two p+ diffusion regions. An n+ contact to epitaxial layer 88 forms the body bias terminal 96. The junction between p-type diffusion region 90 and n-type epitaxial layer 88 is always reverse biased. A positive voltage applied to body bias terminal 96 varies the width of the depletion region formed at the junction, thereby modulating the resistance of resistor 82.

In reference circuit 20, Resistors R1b and R2 have fixed resistance. A fixed resistance diffusion resistor is realized by tying the body bias terminals of the resistor to the most positive end of the resistor. Referring to Figure 2, the body bias terminal of resistor R1b is connected to node 28 which is one end of resistor R1b. Similarly, the body bias terminal of resistor R2 is connected to node 30 which is one end of resistor R2. Resistor R1a, on the other hand, has a variable resistance. The body terminal of resistor R1a is connected to node 26. Thus, the resistance of resistor R1a is modulated by the collector voltage of transistor Q1, denoted VC1.

In the present embodiment and in the embodiments which follow, resistors R1 and R2, including its separate resistive components, are constructed as diffusion resistors such as resistor 82 of Figure 5. However, this is illustrative only and is not intended to limit the present invention to a resistor structure as that shown in Figure 5 only. In fact, one skilled in the art will appreciate that other diffused resistor or junction resistor structures such as those described in Gray and Meyer can be used. Also, resistor structures other than a junction resistor can also be used. Moreover, one skilled in the art will appreciate that the variable resistors in the embodiments of the present invention can be any type of variable resistors whose resistance can be controlled by a voltage.

Output voltage Vout (node 30) of voltage reference circuit 20 is the sum of the voltage across resistor R2 (denoted VR2) and the base to emitter voltage VBE2 of transistor Q2. Voltage reference circuit 20 operates in a manner similar to voltage reference circuit 10 of Figure 1 to generate a bandgap reference voltage (voltage Vout) of approximately 1.25 volts and having substantially zero temperature coefficient.

In accordance with the present invention, voltage reference circuit 20 ensures that voltage Vout is independent of variations in the supply voltage Vs by maintaining the current Ic2 flowing through resistor R2 and transistor Q2 constant, despite variations in the supply voltage Vs. Current IC2 is mirrored by the current mirror of reference circuit 20 (i.e., transistors M1 and M2) from a current IC1 flowing in the collector terminal of transistor Q1. When well-known start-up circuitry (not shown) is employed to set reference circuit 20 to the desired operating point, currents IC1 and IC2 are equal but not to zero. Therefore, as long as current IC1 is held constant with respect to variations in the supply voltage Vs, then current Ic2 is also held constant and the output voltage Vout does not vary with voltage Vs. In reference circuit 20, current IC1 is kept constant by adjusting the base to emitter voltage of transistor Q1, VBE1, through the operation of variable resistor R1a.

In operation, as the supply voltage Vs (node 22) varies, the gate to source voltage Vgs of transistor M1 is kept relatively constant since current IC1 is relatively constant. Therefore, the collector voltage VC1 of transistor Q1 (node 26) varies with voltage Vs. Without the novel voltage compensation technique of the present invention, current IC1 of transistor Q1 will vary due to the changes in collector voltage VC1 which, in turn, causes current IC2 to also vary. However, in the present embodiment, variations in current IC1, resulting from a finite Early voltage, are prevented by adjusting the resistance of resistor R1a which adjusts the base to emitter voltage VBE1 of transistor Q1. In this manner, a constant base voltage VB at the base of transistor Q1 is maintained and both currents IC1 and IC2 are kept constant despite variations in supply voltage Vs.

As described above, current IC1 is kept constant through the operation of variable resistor R1a. In reference circuit 20, because the body bias terminal of resistor R1a is connected to node 26, any variation in collector voltage VC1 of transistor Q1 is applied to resistor R1a. If collector voltage VC1 increases, the body bias to resistor R1a increases, causing the resistance of resistor R1a to increase as well. The resistance of resistor R1a is increased by an amount sufficient to maintain the required constant current IC1 through the resistor. As a result, the voltage across resistor R1a, VR1a, increases. The increase in voltage VR1a causes a corresponding decrease in voltage VBE1 of transistor Q1. Voltage VBE1 of transistor Q1 is decreased just enough to offset any increase in IC1 due to the increase in collector voltage VC1. Thus, current IC1 is restored to a constant value and base voltage VB is kept constant. Current IC2, mirrored from current IC1, is also kept constant despite variations in supply voltage Vs so that output voltage Vout (node 30) is also independent of variations in supply voltage Vs.

In the present embodiment, resistor R1 is shown as including two resistive components, R1a and R1b, of which only resistor R1a has variable resistance. The present embodiment permits only a portion of the total resistance of resistor R1 to be varied to compensate for variations in the collector voltage VC1 due to variations in supply voltage Vs. The present embodiment has the advantage of limiting the magnitude of change in the voltage across R1, thus providing for fine control of the compensating voltage VR1a. In another embodiment, resistor R1 may include only a single variable resistor. In such an embodiment, the entire resistance of resistor R1 is varied by the collector voltage VC1 (node 26), creating a larger change in the compensating voltage VR1 (the voltage across the entire resistor R1).

Furthermore, in the present embodiment, the body bias terminal of resistor R1a is connected to the collector terminal of transistor Q1. In another embodiment, the body bias terminal of resistor R1 or resistor R1a (if resistor R1 is split) can be connected directly to the supply voltage Vs. Because the voltage across transistor M1, i.e., the drain to source voltage Vds, remains constant as supply voltage Vs varies, the entire variation in supply voltage Vs is reflected at the collector terminal of transistor Q1. Thus, the resistance of resistor R1 can be modulated by either the collector voltage of transistor Q1 or the supply voltage Vs directly to obtain the same magnitude of change in resistance.

The derivation of the design equation for voltage reference circuit 20 of the present invention will now be described. Referring to Figure 2, the base voltage VB of transistor Q2 is given by: V B = V B E 1 + V R 1

where VR1 is the voltage across resistor R1 and VBE1 is the base to emitter voltage of transistor Q1. Voltages VBE1 and VR1 are varied in response to variations in supply voltage Vs in order to keep base voltage VB constant. Voltage VR1 is varied while still maintaining a constant current IC1 flowing through resistor R1 by varying its resistance accordingly. A parameter a is defined as the first order voltage coefficient of resistor R1. Because collector voltage VC1 (node 26) controls the body bias of resistor R1, the resistance of resistor R1 as a function of the collector to emitter voltage VCE1 of transistor Q1 is given by: R 1 = R 1 0 ( 1 + a V C E 1 )

where R10 is the resistance of resistor R1 at zero-volt body bias. A fractional change in voltage VR1, termed &Dgr;VR1, is given by: &Dgr; V R 1 V R 1 = a V C E 1 , assuming that the current through the resistor is kept constant. As described above, the magnitude of change in voltage VR1 for a given VCE1 can be controlled by dividing resistor R1 into resistors R1a and R1b and applying the body bias of voltage VCE1 to resistor R1a only as shown in Figure 2. For the embodiment shown in Figure 2, the fractional change in voltage VR1 becomes: &Dgr; V R 1 V R 1 = f a V C E 1 , where f = R 1 a R 1 a + R 1 b . As described above, voltage VR1 equals to a voltage &Dgr;VBE which is the difference in the base to emitter voltages of transistors Q1 and Q2. The voltage &Dgr;VBE is given by the equation: &Dgr; V B E = k T q ln ( n ) . Therefore, the change in voltage VR1 can be expressed as: &Dgr; V R 1 = f a V C E 1 k T q ln ( n ) . On the other hand, the change in the base to emitter voltage of transistor Q1, &Dgr;VBE1, required to offset the increase in the collect current due to the Early effect is derived as follows. The dependence of collector current Ic1 of transistor Q1 on voltage VCE1 can be expressed as: I C 1 = I 0 ( 1 + V C E 1 V A )

where I0 is the extrapolated collector current at VCE1=0 volt and VA is the Early voltage of transistor Q1. The change in base to emitter voltage as a function of the collector current is given by: &Dgr; V B E 1 = k T q ln ( I C E 1 I 0 ) = k T q ln ( 1 + V C E 1 V A ) .

Expanding the logarithmic term and making the assumptions that VCE1 is typically limited to about 6 volts and VA is typically over 100 volts, voltage &Dgr;VBE1 can be approximated as: &Dgr; V B E 1 = k T q ( V C E 1 V A ) .

The above equation describes how much change in voltage VBE1 is required to keep IC1 through transistor Q1 constant, and this change must be equal to the change in voltage across resistor R1. Equating voltage &Dgr;VR1 and &Dgr;VBE1 provides the design equation required to keep the collect current IC1 and the base voltage VB constant. The design equation is expressed as: f = 1 a V A ln ( n ) . Since f is a maximum of one, an adequate adjustment range is achieved if the voltage coefficient a of resistor R1 is: a 1 V A ln ( n ) . For typical values of Early voltage VA of 100 volts and a transistor size ratio n of 4, a is required to be greater than or equal to 0.0072 which is a condition easily achieved in standard integrated circuit manufacturing processes.

In the present embodiment, the transistor size ratio n is in the range of 2 to 10, typically n is 4. When current IC1 is set to be 1 µA, the resistance of resistor R1 is in the range of 18 k&OHgr; to 60 k&OHgr;, typically the resistance is 36 k&OHgr;. The resistance of resistor R2 is approximately 500 k&OHgr;.

Voltage reference circuit 20 of the present embodiment provides a reference voltage Vout that is temperature independent and supply voltage independent. Furthermore, voltage reference circuit 20 improves line regulation without adding voltage or current burdens on the circuit. The architecture of reference circuit 20 utilizes only two current paths, thereby ensuring minimal power consumption in operation. Voltage reference circuit 20 is particularly suitable for use in applications where minimal power consumption is required, such as a battery operated voltage monitor circuit.

According to a second embodiment of the present invention, the current consumption of reference circuit 20 is further reduced by making the size of transistor Q1 equal to the size of transistor Q2, i.e., the transistor size ratio n is one. Instead, the size of transistor M2 is made to be n times larger than the size of transistor M1 to provide the proper current density ratio of currents IC1 and IC2. The resistance of resistor R1 is also made n times larger than in the first embodiment. In this manner, a reduction of (n-1)/2n in total supply current is realized.

Figure 3 is a circuit schematic of a voltage reference circuit 50 according to a third embodiment of the present invention. In the second embodiment described above, because the resistance of resistor R1 needs to be made n times larger than in the first embodiment, resistor R1 consumes a much larger device area in the fabrication of the reference circuit, thus increasing manufacturing cost. In accordance with the third embodiment of the present invention, the sizes of transistors Q1 and Q2 are made equal to further reduce current consumption; however, resistor R1 is repositioned so that its resistance can be maintained at the same value as in the first embodiment. The third embodiment of the present invention achieves further reduction in power consumption without the corresponding increase in device area and production cost.

Referring to Figure 3, voltage reference circuit 50 includes bipolar transistors Q1 and Q2, having equal sizes, and a current mirror formed by PMOS transistors M1 and M2 having unequal sizes. Specifically, the size (channel width) of transistor M2 is n times larger than the size of transistor M1. The base terminal of transistor Q1 is connected to the collector terminal of transistor Q2 (node 59). Reference circuit 50 further includes a resistor R1 and a resistor R2 which are connected in series between voltage output node 60 and the collector terminal of transistor Q2 (node 59). The base terminal of transistor Q2 is connected to a node 56, between resistor R1 and resistor R2.

Resistor R1 of reference circuit 50 includes two resistive components, R1a and R1b, of which resistor R1a has variable resistance. The body bias terminal of resistor R1a is tied to supply voltage Vs (node 52). Thus, the resistance of resistor R1a is modulated by the supply voltage Vs. Resistor R1b has its body bias terminal tied to one end of the resistor (node 58), thus resistor R1b has fixed resistance. Resistor R2 also has its body bias terminal tied to one end of the resistor (node 60), thus resistor R2 also has fixed resistance. In the present embodiment, resistor R1 is split into two resistive components of which only one has variable resistance. As described above in reference to circuit 20, resistor R1 can be a single resistor having its entire resistance being variable.

In the present embodiment, resistor R1 has been repositioned from the IC1 current path to the IC2 current path to take advantage of the larger current flowing in transistor Q2. Therefore, resistor R1 can be made the same size as in the first embodiment (reference circuit 20 of Figure 2) even though the sizes of transistor Q1 and Q2 have been made equal.

In reference circuit 50 of Figure 3, currents IC1 and IC2 are not equal in operation as in the previous embodiments. Current IC2 is made n times greater than current IC1 to create the difference in current densities in transistors Q1 and Q2 needed to generate the difference in base to emitter voltages, &Dgr;VBE. In reference circuit 50, &Dgr;VBE appears across resistor R1 between nodes 56 and 59.

Reference circuit 50 operates to keep current IC1 constant by adjusting the base to emitter voltage VBE1 of transistor Q1 through the operation of variable resistor R1. Because the resistance of resistor R1 is modulated by supply voltage Vs, as voltage Vs varies, the resistance of resistor R1 varies, and voltage VR1 across the resistor also varies accordingly. The increase in voltage VR1 causes the voltage applied to the base terminal of transistor Q1 to decrease. As a result, the base to emitter voltage VBE1 of transistor Q1 is adjusted as the supply voltage Vs varies to compensate for any variation in current IC1 due to variations in the supply voltage Vs.

For example, if supply voltage Vs increases, the resistance of resistor R1a is increased due to the increase in supply voltage Vs. As a result, voltage VR1 (between nodes 56 and 59) increases, causing VBE1 of transistor Q1 to decrease. The decrease in voltage VBE1 leads to a decrease in collector current IC1 which offsets any increase in current IC1 due to the increase in supply voltage Vs. Therefore, currents IC1 and IC2 are thus maintained constant, and output voltage Vout (node 60) is also maintained constant despite variations in supply voltage Vs.

In the above described embodiments, resistor R1 is divided so only part of resistor R1 is variable. However, it is often difficult to divide resistor R1 into two components because its resistance value is much smaller than resistor R2. Alternately, it is often more convenient to divide resistor R2 into two components while still maintaining resistance match with resistor R1.

Figure 4 is a circuit schematic of a voltage reference circuit 70 according to a fourth embodiment of the present invention. Reference circuit 70 is constructed in the same manner as reference circuit 50 of Figure 3. However, in reference circuit 70, resistor R1 has a single variable resistive component, and the body bias of resistor R1 is applied to the entire resistor. The resistance of resistor R1 is modulated by supply voltage Vs (node 72). On the other hand, resistor R2 of reference circuit 70 is split into two resistive components, R2a and R2b. Resistor R2a is a variable-resistance resistor having its body bias terminal connected to supply voltage Vs (node 72). Resistor R2b is a fixed-resistance resistor having its body bias terminal connected to one end of the resistor (node 76).

In reference circuit 70, the entire resistance of resistor R1 is being modulated in response to variation in supply voltage Vs, which results in an overadjustment of the collector current IC1 in transistor Q1. Specifically, when the supply voltage Vs increases, the entire resistance of resistor R1 is being modulated and voltage VR1 increases. The base to emitter voltage VBE1 of transistor Q1 is being decreased more than necessary to compensate for any increase in current IC1. As a result, IC1 and IC2 actually decrease as supply voltage Vs increases. Reference circuit 70 compensates for the overadjustment through the operation of variable resistor R2a. By providing resistor R2a having its body bias also controlled by supply voltage Vs, voltage Vout (node 80) is restored to a level sufficient to compensate for the decrease in current IC2 caused by the overadjustment by resistor R1. Reference circuit 70 is thus able to maintain a constant output voltage Vout (node 80) that is independent of variations in supply voltage Vs.

In the voltage reference circuits of the above described embodiments, improvement in line regulation characteristics of up to 40 times over conventional voltage reference circuits have been observed. In one embodiment, the output reference voltage is maintained constant over variations in supply voltage of 1.5 to 6 volts. In the above analysis, a constant Early voltage VA is assumed. In practice, the Early voltage of a transistor may not be constant and may vary as much as ±50% from its nominal value over variations in the process. In such case, the design parameter f can be adjusted using any standard trim technique. However, even if trimming is not used to compensate for variations in Early voltage, simulation results reveal that the reference circuit of the above embodiments improves line regulation characteristics by a minimum of 70% over conventional reference circuits.

In the present description, start-up circuitry for the reference circuits are not shown. However, one skilled in the art will appreciate that any conventional start-up circuitry may be used to bias the voltage reference circuits of the present inventions into the proper operation point.


Anspruch[de]
Spannungsreferenzschaltung (20) mit: einem Stromspiegel, der elektrisch an eine erste Versorgungsspannung (22) angeschlossen ist, wobei der Stromspiegel einen ersten Stromanschluss (26) und einen zweiten Stromanschluss (30) aufweist; einem ersten Transistor (Q1), der einen ersten stromführenden Anschluss, einen zweiten stromführenden Anschluss, der an den ersten Stromanschluss des Stromspiegels angeschlossen ist, und einen Steueranschluss hat; einem zweiten Transistor (Q2), der einen ersten stromführenden Anschluss, der mit einer zweiten Versorgungsspannung (24) verbunden ist, einen zweiten stromführenden Anschluss und einen Steueranschluss hat, der an den zweiten stromführenden Anschluss angeschlossen ist, wobei der Steueranschluss auch mit dem Steueranschluss des ersten Transistors verbunden ist; einem ersten Widerstand (R1), angeschlossen zwischen dem ersten stromführenden Anschluss des ersten Transistors und der zweiten Versorgungsspannung; und einem zweiten Widerstand (R2), angeschlossen zwischen dem zweiten Stromanschluss des Stromspiegels und dem zweiten stromführenden Anschluss des zweiten Transistors, dadurch gekennzeichnet, dass der erste Widerstand einen variablen Widerstandswert hat, wobei der Widerstandswert durch eine erste Vorspannung in Bezug auf die erste Versorgungsspannung moduliert wird. Schaltung nach Anspruch 1, wobei der zweite Stromanschluss des Stromspiegels eine Bezugsspannung (Vout) zur Verfügung stellt, und wobei die Bezugsspannung proportional zu einer Bandabstandsspannung ist und im Wesentlichen über einen ersten Temperaturbereich und einen ersten Spannungsbereich der ersten Versorgungsspannung konstant ist. Schaltung nach Anspruch 1, wobei die erste Vorspannung eine Spannung am zweiten stromführenden Anschluss (26) des ersten Transistors ist. Schaltung nach Anspruch 1, wobei die erste Vorspannung die erste Versorgungsspannung ist. Schaltung nach Anspruch 1, wobei der erste Widerstand umfasst: einen dritten Widerstand (R1a), der einen variablen Widerstandswert hat, der von der ersten Vorspannung moduliert wird; und einen vierten Widerstand (R1 b), der einen festen Widerstandswert hat. Schaltung nach Anspruch 5, wobei die erste Vorspannung eine Spannung am zweiten stromführenden Anschluss (26) des ersten Transistors ist. Schaltung nach Anspruch 5, wobei die erste Vorspannung die erste Versorgungsspannung ist. Schaltung nach Anspruch 5, wobei die zweiten, dritten und vierten Widerstände Diffusionswiderstände sind. Schaltung nach Anspruch 8, wobei der Widerstandswert des dritten Widerstands moduliert wird durch das Abgleichen einer Körpervorspannung des Widerstands. Schaltung nach Anspruch 1, wobei die ersten und zweiten Widerstände Diffusionswiderstände sind. Schaltung nach Anspruch 10, wobei der Widerstandswert des ersten Widerstands moduliert wird durch das Abgleichen einer Körpervorspannung des Widerstands. Schaltung nach Anspruch 1, wobei die ersten und zweiten Transistoren bipolare Transistoren sind. Schaltung nach Anspruch 12, wobei die ersten und zweiten Transistoren bipolare NPN Transistoren sind. Schaltung nach Anspruch 1, wobei der Stromspiegel umfasst: einen dritten Transistor (M1), der einen ersten stromführenden Anschluss, der an der ersten Versorgungsspannung angeschlossen ist, und einen zweiten stromführenden Anschluss hat, der mit einem Steueranschluss und dem zweiten stromführenden Anschluss des ersten Transistors verbunden ist; und einen vierten Transistor (M2), der einen Steueranschluss, der an den Steueranschluss des dritten Transistors angeschlossen ist, einen ersten stromführenden Anschluss, der mit der ersten Versorgungsspannung verbunden, ist und einen zweiten stromführenden Anschluss hat, der an den Ausgangsanschluss der Schaltung angeschlossen ist. Schaltung nach Anspruch 14, wobei die dritten und vierten Transistoren MOS Transistoren sind. Schaltung nach Anspruch 15, wobei die dritten und vierten Transistoren P- Kanal MOS Transistoren sind. Schaltung nach Anspruch 14, wobei der erste Transistor eine erste Größe hat und der zweite Transistor eine zweite Größe hat, wobei die erste Größe n mal größer ist als die zweite Größe, und wobei der dritte Transistor eine dritte Größe hat und der vierte Transistor eine vierte Größe hat, wobei die dritte und vierte Größe im Wesentlichen gleich sind. Schaltung nach Anspruch 17, wobei die ersten und zweiten Transistoren bipolare NPN Transistoren sind und jede der ersten und zweiten Größe einem Emittergebiet jedes der Transistoren zugeordnet ist. Schaltung nach Anspruch 14, wobei der erste Transistor eine erste Größe hat und der zweite Transistor eine zweite Größe hat, wobei die erste Größe im Wesentlichen gleich der zweiten Größe ist, und wobei der dritte Transistor eine dritte Größe hat und der vierte Transistor eine vierte Größe hat, wobei die vierte Größe n mal größer ist als die dritte Größe. Schaltung nach Anspruch 19, wobei ein Betriebsstrom der Schaltung weniger als 1 µA ist. Spannungsreferenzschaltung (50, 70) mit: einem Stromspiegel, der elektrisch an eine erste Versorgungsspannung (52, 72) angeschlossen ist, wobei der Stromspiegel einen ersten Stromanschluss und einen zweiten Stromanschluss (60, 80) aufweist; einem ersten Transistor (Q1 der einen ersten stromführenden Anschluss, der an eine zweite Versorgungsspannung (54, 74) angeschlossen ist, einen zweiten stromführenden Anschluss, der an den ersten Stromanschluss des Stromspiegels angeschlossen ist, und einen Steueranschluss hat; einem zweiten Transistor (Q2), der einen ersten stromführenden Anschluss, der mit der zweiten Versorgungsspannung verbunden ist, einen zweiten stromführenden Anschluss (59, 74), der mit dem Steueranschluss des ersten Transistors verbunden ist, und einen Steueranschluss hat, der an einen ersten Knoten (56, 78) angeschlossen ist, einem ersten Widerstand (R1), angeschlossen zwischen dem zweiten stromführenden Anschluss des zweiten Transistors und dem ersten Knoten; und einem zweiten Widerstand (R2), angeschlossen zwischen dem ersten Knoten und dem zweiten Stromanschluss des Stromspiegels, dadurch gekennzeichnet, dass der erste Widerstand einen variablen Widerstandswert hat, wobei der Widerstandswert durch eine erste Vorspannung in Bezug auf die erste Versorgungsspannung moduliert wird. Schaltung nach Anspruch 21, wobei der zweite Stromanschluss des Stromspiegels eine Bezugsspannung (Vout) zur Verfügung stellt, und wobei die Bezugsspannung proportional zu einer Bandabstandsspannung ist und im Wesentlichen über einen ersten Temperaturbereich und einen ersten Spannungsbereich der ersten Versorgungsspannung konstant ist. Schaltung nach Anspruch 21, wobei die erste Vorspannung die erste Versorgungsspannung ist. Schaltung nach Anspruch 21, wobei der erste Widerstand umfasst: einen dritten Widerstand (R1a), der einen variablen Widerstandswert hat, der von der ersten Vorspannung moduliert wird; und einen vierten Widerstand (R1b), der einen festen Widerstandswert hat. Schaltung nach Anspruch 24, wobei die erste Vorspannung die erste Versorgungsspannung ist. Schaltung nach Anspruch 24, wobei die zweiten, dritten und vierten Widerstände Diffusionswiderstände sind. Schaltung nach Anspruch 26, wobei der Widerstandswert des dritten Widerstands moduliert wird durch das Abgleichen einer Körpervorspannung des Widerstands. Schaltung nach Anspruch 21, wobei die ersten und zweiten Widerstände Diffusionswiderstände sind. Schaltung nach Anspruch 28, wobei der Widerstandswert des ersten Widerstands moduliert wird durch das Abgleichen einer Körpervorspannung des Widerstands. Schaltung nach Anspruch 21, wobei die ersten und zweiten Transistoren bipolare Transistoren sind. Schaltung nach Anspruch 30, wobei die ersten und zweiten Transistoren bipolare NPN Transistoren sind. Schaltung nach Anspruch 21, wobei der Stromspiegel umfasst: einen dritten Transistor (M1), der einen ersten stromführenden Anschluss, der an der ersten Versorgungsspannung angeschlossen ist, und einen zweiten stromführenden Anschluss hat, der mit einem Steueranschluss und dem zweiten stromführenden Anschluss des ersten Transistors verbunden ist; und einen vierten Transistor (M2), der einen Steueranschluss, der an den Steueranschluss des dritten Transistors angeschlossen ist, einen ersten stromführenden Anschluss, der mit der ersten Versorgungsspannung verbunden ist, und einen zweiten stromführenden Anschluss hat, der an den Ausgangsanschluss der Schaltung angeschlossen ist. Schaltung nach Anspruch 32, wobei die dritten und vierten Transistoren MOS Transistoren sind. Schaltung nach Anspruch 33, wobei die dritten und vierten Transistoren P- Kanal MOS Transistoren sind. Schaltung nach Anspruch 34, wobei die ersten und zweiten Transistoren bipolare NPN Transistoren sind. Schaltung nach Anspruch 32, wobei der erste Transistor eine erste Größe hat und der zweite Transistor eine zweite Größe hat, wobei die erste Größe im Wesentlichen gleich der zweiten Größe ist, und wobei der dritte Transistor eine dritte Größe hat und der vierte Transistor eine vierte Größe hat, wobei die vierte Größe n mal größer ist als die dritte Größe. Schaltung nach Anspruch 21, wobei der zweite Widerstand einen variablen Widerstandswert hat, wobei der Widerstandswert von der ersten Vorspannung moduliert wird Schaltung nach Anspruch 37, wobei die erste Vorspannung eine Spannung am zweiten stromführenden Anschluss des ersten Transistors ist. Schaltung nach Anspruch 37, wobei die erste Vorspannung die erste Versorgungsspannung ist. Schaltung nach Anspruch 37, wobei der zweite Widerstand umfasst: einen dritten Widerstand (R2a), der einen variablen Widerstandswert hat, der von der ersten Vorspannung moduliert wird; und einen vierten Widerstand (R2b), der einen festen Widerstandswert hat. Schaltung nach Anspruch 40, wobei die erste Vorspannung die erste Versorgungsspannung ist. Schaltung nach Anspruch 21, wobei ein Betriebsstrom der Schaltung weniger als 1 µA ist.
Anspruch[en]
A voltage reference circuit (20) comprising: a current mirror electrically coupled to a first supply voltage (22), said current mirror having a first current terminal (26) and a second current terminal (30); a first transistor (Q1) having a first current handling terminal, a second current handling terminal coupled to said first current terminal of said current mirror, and a control terminal; a second transistor (Q2) having a first current handling terminal coupled to a second supply voltage (24), a second current handling terminal, and a control terminal coupled to said second current handling terminal, said control terminal also coupled to said control terminal of said first transistor; a first resistor (R1) coupled between said first current handling terminal of said first transistor and said second supply voltage; and a second resistor (R2) coupled between said second current terminal of said current mirror and said second current handling terminal of said second transistor, characterized in that said first resistor has a variable resistance, said resistance being modulated by a first bias voltage related to said first supply voltage. The circuit of Claim 1, wherein said second current terminal of said current mirror provides a reference voltage (Vout), and wherein said reference voltage is proportional to a bandgap voltage and is substantially constant over a first temperature range and a first voltage range of said first supply voltage. The circuit of Claim 1, wherein said first bias voltage is a voltage at said second current handling terminal (26) of said first transistor. The circuit of Claim 1, wherein said first bias voltage is said first supply voltage. The circuit of Claim 1, wherein said first resistor comprises: a third resistor (R1a) having a variable resistance being modulated by said first bias voltage; and a fourth resistor (R1b) having a fixed resistance. The circuit of Claim 5, wherein said first bias voltage is a voltage at said second current handling terminal (26) of said first transistor. The circuit of Claim 5, wherein said first bias voltage is said first supply voltage. The circuit of Claim 5, wherein said second, third, and fourth resistors are diffusion resistors. The circuit of Claim 8, wherein said resistance of said third resistor is modulated by adjusting a body bias voltage of said resistor. The circuit of Claim 1, wherein said first and second resistors are diffusion resistors. The circuit of Claim 10, wherein said resistance of said first resistor is modulated by adjusting a body bias voltage of said resistor. The circuit of Claim 1, wherein said first and second transistors are bipolar transistors. The circuit of Claim 12, wherein said first and second transistors are NPN bipolar transistors. The circuit of Claim 1, wherein said current mirror comprises: a third transistor (M1) having a first current handling terminal coupled to said first supply voltage, and a second current handling terminal coupled to a control terminal and to said second current handling terminal of said first transistor; and a fourth transistor (M2) having a control terminal coupled to said control terminal of said third transistor, a first current handling terminal coupled to said first supply voltage, and a second current handling terminal coupled to said output terminal of said circuit. The circuit of Claim 14, wherein said third and fourth transistors are MOS transistors. The circuit of Claim 15, wherein said third and fourth transistors are P-channel MOS transistors. The circuit of Claim 14, wherein said first transistor has a first size and said second transistor has a second size, said first size being n times greater than said second size, and wherein said third transistor has a third size and said fourth transistor has a fourth size, said third and fourth sizes being substantially equal. The circuit of Claim 17, wherein said first and second transistors are NPN bipolar transistors, and each of said first and second sizes is associated with an emitter area of each of said transistors. The circuit of Claim 14, wherein said first transistor has a first size and said second transistor has a second size, said first size being substantially equal to said second size, and wherein said third transistor has a third size and said fourth transistor has a fourth size, said fourth size being n times greater than said third size. The circuit of Claim 19, wherein an operating current of said circuit is less than 1 µA. A voltage reference circuit (50, 70) comprising: a current mirror electrically coupled to a first supply voltage (52, 72), said current mirror having a first current terminal and a second current terminal (60, 80); a first transistor (Q1) having a first current handling terminal coupled to a second supply voltage (54, 74), a second current handling terminal coupled to said first current terminal of said current mirror, and a control terminal; a second transistor (Q2) having a first current handling terminal coupled to said second supply voltage, a second current handling terminal (59, 74)coupled to said control terminal of said first transistor, and a control terminal coupled to a first node (56, 78); a first resistor (R1) coupled between said second current handling terminal of said second transistor and said first node; and a second resistor (R2) coupled between said first node and said second current terminal of said current mirror, characterized in that said first resistor has a variable resistance, said resistance being modulated by a first bias voltage related to said first supply voltage. The circuit of Claim 21, wherein said second current terminal of said current mirror provides a reference voltage (Vout), and wherein said reference voltage is proportional to a bandgap voltage and is substantially constant over a first temperature range and a first voltage range of said first supply voltage. The circuit of Claim 21, wherein said first bias voltage is said first supply voltage. The circuit of Claim 21, wherein said first resistor comprises: a third resistor (R1a) having a variable resistance being modulated by said first bias voltage, and a fourth resistor (R1b) having a fixed resistance. The circuit of Claim 24, wherein said first bias voltage is said first supply voltage. The circuit of Claim 24, wherein said second, third, and fourth resistors are diffusion resistors. The circuit of Claim 26, wherein said resistance of said third resistor is modulated by adjusting a body bias voltage of said resistor. The circuit of Claim 21, wherein said first and second resistors are diffusion resistors. The circuit of Claim 28, wherein said resistance of said first resistor is modulated by adjusting a body bias voltage of said resistor. The circuit of Claim 21, wherein said first and second transistors are bipolar transistors. The circuit of Claim 30, wherein said first and second transistors are NPN bipolar transistors. The circuit of Claim 21, wherein said current mirror comprises: a third transistor (M1) having a first current handling terminal coupled to said first supply voltage, and a second current handling terminal coupled to a control terminal and to said second current handling terminal of said first transistor; and a fourth transistor (M2) having a control terminal coupled to said control terminal of said third transistor, a first current handling terminal coupled to said first supply voltage, and a second current handling terminal coupled to said output terminal of said circuit. The circuit of Claim 32, wherein said third and fourth transistors are MOS transistors. The circuit of Claim 33, wherein said third and fourth transistors are P-channel MOS transistors. The circuit of Claim 34, wherein said first and second transistors are NPN bipolar transistors. The circuit of Claim 32, wherein said first transistor has a first size and said second transistor has a second size, said first size being substantially equal to said second size, and wherein said third transistor has a third size and said fourth transistor has a fourth size, said fourth size being n times greater than said third size. The circuit of Claim 21, wherein said second resistor has a variable resistance, said resistance being modulated by said first bias voltage. The circuit of Claim 37, wherein said first bias voltage is a voltage at said second current handling terminal of said first transistor. The circuit of Claim 37, wherein said first bias voltage is said first supply voltage. The circuit of Claim 37, wherein said second resistor comprises: a third resistor (R2a) having a variable resistance being modulated by said first bias voltage, and a fourth resistor (R2b) having a fixed resistance. The circuit of Claim 40, wherein said first bias voltage is said first supply voltage. The circuit of Claim 21, wherein an operating current of said circuit is less than 1 µA.
Anspruch[fr]
Circuit de tension de référence (20) comprenant : un miroir de courant couplé électriquement à une première tension d'alimentation (22), ledit miroir de courant ayant une première borne de courant (26) et une deuxième borne de courant (30) ; un premier transistor (Q1) ayant une première borne admettant un courant, une deuxième borne admettant un courant couplée à ladite première borne de courant dudit miroir de courant, et une borne de commande ; un deuxième transistor (Q2) ayant une première borne admettant un courant couplée à une deuxième tension d'alimentation (24), une deuxième borne admettant un courant, et une borne de commande couplée à ladite deuxième borne admettant un courant, ladite borne de commande étant également couplée à ladite borne de commande dudit premier transistor ; une première résistance (R1) couplée entre ladite première borne admettant un courant dudit premier transistor et ladite deuxième tension d'alimentation ; et une deuxième résistance (R2) couplée entre ladite deuxième borne de courant dudit miroir de courant et ladite deuxième borne admettant un courant dudit deuxième transistor, caractérisé en ce que : ladite première résistance présente une valeur de résistance variable, ladite valeur de résistance étant modulée par une première tension de polarisation liée à ladite première tension d'alimentation. Circuit selon la revendication 1, dans lequel ladite deuxième borne de courant dudit miroir de courant fournit une tension de référence (Vout), et dans lequel ladite tension de référence est proportionnelle à une tension de bande interdite et est sensiblement constante sur une première gamme de températures et une première gamme de tensions de ladite première tension d'alimentation. Circuit selon la revendication 1, dans lequel ladite première tension de polarisation est une tension relevée à ladite deuxième borne admettant un courant (26) dudit premier transistor. Circuit selon la revendication 1, dans lequel ladite première tension de polarisation est ladite première tension d'alimentation. Circuit selon la revendication 1, dans lequel ladite première résistance comprend : une troisième résistance (R1a) ayant une valeur de résistance variable modulée par ladite première tension de polarisation ; et une quatrième résistance (R1b) ayant une valeur de résistance fixe. Circuit selon la revendication 5, dans lequel ladite première tension de polarisation est une tension relevée à ladite deuxième borne admettant un courant (26) dudit premier transistor. Circuit selon la revendication 5, dans lequel ladite première tension de polarisation est ladite première tension d'alimentation. Circuit selon la revendication 5, dans lequel lesdites deuxième, troisième et quatrième résistances sont des résistances de diffusion. Circuit selon la revendication 8, dans lequel ladite valeur de résistance de ladite troisième résistance est modulée grâce à l'ajustement d'une tension de polarisation de corps de ladite résistance. Circuit selon la revendication 1, dans lequel lesdites première et deuxième résistances sont des résistances de diffusion. Circuit selon la revendication 10, dans lequel ladite valeur de résistance de ladite première résistance est modulée grâce à l'ajustement d'une tension de polarisation de corps de ladite résistance. Circuit selon la revendication 1, dans lequel lesdits premier et deuxième transistors sont des transistors bipolaires. Circuit selon la revendication 12, dans lequel lesdits premier et deuxième transistors sont des transistors bipolaires NPN. Circuit selon la revendication 1, dans lequel ledit miroir de courant comprend : un troisième transistor (M1) ayant une première borne admettant un courant couplée à ladite première tension d'alimentation, et une deuxième borne admettant un courant couplée à une borne de commande et à ladite deuxième borne admettant un courant dudit premier transistor ; et un quatrième transistor (M2) ayant une borne de commande couplée à ladite borne de commande dudit troisième transistor, une première borne admettant un courant couplée à ladite première tension d'alimentation, et une deuxième borne admettant un courant couplée à ladite borne de sortie dudit circuit. Circuit selon la revendication 14, dans lequel lesdits troisième et quatrième transistors sont des transistors MOS. Circuit selon la revendication 15, dans lequel lesdits troisième et quatrième transistors sont des transistors MOS à canal P. Circuit selon la revendication 14, dans lequel ledit premier transistor présente une première taille et ledit deuxième transistor présente une deuxième taille, ladite première taille étant n fois supérieure à ladite deuxième taille, et dans lequel ledit troisième transistor présente une troisième taille et ledit quatrième transistor présente une quatrième taille, lesdites troisième et quatrième tailles étant sensiblement égales. Circuit selon la revendication 17, dans lequel lesdits premier et deuxième transistors sont des transistors bipolaires NPN et chacune desdites première et deuxième tailles est associée à une zone d'émetteur de chacun desdits transistors. Circuit selon la revendication 14, dans lequel ledit premier transistor présente une première taille et ledit deuxième transistor présente une deuxième taille, ladite première taille étant sensiblement égale à ladite deuxième taille, et dans lequel ledit troisième transistor présente une troisième taille et ledit quatrième transistor présente une quatrième taille, ladite quatrième taille étant n fois supérieure à ladite troisième taille. Circuit selon la revendication 19, dans lequel un courant de fonctionnement dudit circuit est inférieur à 1 µA. Circuit de tension de référence (50, 70) comprenant : un miroir de courant couplé électriquement à une première tension d'alimentation (52, 72), ledit miroir de courant ayant une première borne de courant et une deuxième borne de courant (60, 80) ; un premier transistor (Q1) ayant une première borne admettant un courant couplée à une deuxième tension d'alimentation (54, 74), une deuxième borne admettant un courant couplée à ladite première borne de courant dudit miroir de courant, et une borne de commande ; un deuxième transistor (Q2) ayant une première borne admettant un courant couplée à ladite deuxième tension d'alimentation, une deuxième borne admettant un courant (59, 74) couplée à ladite borne de commande dudit premier transistor, et une borne de commande couplée à un premier noeud (56, 78) ; une première résistance (R1) couplée entre ladite deuxième borne admettant un courant dudit deuxième transistor et ledit premier noeud ; et une deuxième résistance (R2) couplée entre ledit premier noeud et ladite deuxième borne de courant dudit miroir de courant, caractérisé en ce que : ladite première résistance présente une valeur de résistance variable, ladite valeur de résistance étant modulée par une première tension de polarisation, liée à ladite première tension d'alimentation. Circuit selon la revendication 21, dans lequel ladite deuxième borne de courant dudit miroir de courant fournit une tension de référence (Vout), et dans lequel ladite tension de référence est proportionnelle à une tension de bande interdite et sensiblement constante sur un premier éventail de températures et un premier éventail de tensions de ladite première tension d'alimentation. Circuit selon la revendication 21, dans lequel ladite première tension de polarisation est ladite première tension d'alimentation. Circuit selon la revendication 21, dans lequel ladite première résistance comprend : une troisième résistance (R1a) ayant une valeur de résistance variable modulée par ladite première tension de polarisation, et une quatrième résistance (R1b) ayant une valeur de résistance fixe. Circuit selon la revendication 24, dans lequel ladite première tension de polarisation est ladite première tension d'alimentation. Circuit selon la revendication 24, dans lequel lesdites deuxième, troisième et quatrième résistances sont des résistances de diffusion. Circuit selon la revendication 26, dans lequel ladite valeur de résistance de ladite troisième résistance est modulée grâce à l'ajustement d'une tension de polarisation de corps de ladite résistance. Circuit selon la revendication 21, dans lequel lesdites première et deuxième résistances sont des résistances de diffusion. Circuit selon la revendication 28, dans lequel ladite valeur de résistance de ladite première résistance est modulée grâce à l'ajustement d'une tension de polarisation de corps de ladite résistance. Circuit selon la revendication 21, dans lequel lesdits premier et deuxième transistors sont des transistors bipolaires. Circuit selon la revendication 30, dans lequel lesdits premier et deuxième transistors sont des transistors bipolaires NPN. Circuit selon la revendication 21, dans lequel ledit miroir de courant comprend : un troisième transistor (M1) ayant une première borne admettant un courant couplée à ladite première tension d'alimentation, et une deuxième borne admettant un courant couplée à une borne de commande et à ladite deuxième borne admettant un courant dudit premier transistor ; et un quatrième transistor (M2) ayant une borne de commande couplée à ladite borne de commande dudit troisième transistor, une première borne admettant un courant couplée à ladite première tension d'alimentation, et une deuxième borne admettant un courant couplée à ladite borne de sortie dudit circuit. Circuit selon la revendication 32, dans lequel lesdits troisième et quatrième transistors sont des transistors MOS. Circuit selon la revendication 33, dans lequel lesdits troisième et quatrième transistors sont des transistors MOS à canal P. Circuit selon la revendication 34, dans lequel lesdits premier et deuxième transistors sont des transistors bipolaires NPN. Circuit selon la revendication 32, dans lequel ledit premier transistor présente une première taille et ledit deuxième transistor présente une deuxième taille, ladite première taille étant sensiblement égale à ladite deuxième taille, et dans lequel ledit troisième transistor présente une troisième taille et ledit quatrième transistor présente une quatrième taille, ladite quatrième taille étant n fois supérieure à ladite troisième taille. Circuit selon la revendication 21, dans lequel ladite deuxième résistance présente une valeur de résistance variable, ladite valeur de résistance étant modulée par ladite première tension de polarisation. Circuit selon la revendication 37, dans lequel ladite première tension de polarisation est une tension relevée à ladite deuxième borne admettant un courant dudit premier transistor. Circuit selon la revendication 37, dans lequel ladite première tension de polarisation est ladite première tension d'alimentation. Circuit selon la revendication 37, dans lequel ladite deuxième résistance comprend : une troisième résistance (R2a) ayant une valeur de résistance variable modulée par ladite première tension de polarisation, et une quatrième résistance (R2b) ayant une valeur de résistance fixe. Circuit selon la revendication 40, dans lequel ladite première tension de polarisation est ladite première tension d'alimentation. Circuit selon la revendication 21, dans lequel un courant de fonctionnement dudit circuit est inférieur à 1 µA.






IPC
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