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Dokumentenidentifikation EP1049157 26.04.2007
EP-Veröffentlichungsnummer 0001049157
Titel Herstellungsverfahren für vergrabene Kanäle und Hohlräume in Halbleiterscheiben
Anmelder STMicroelectronics S.r.l., Agrate Brianza, Mailand/Milano, IT
Erfinder Barlocchi, Gabriele, 20010 Cornaredo, IT;
Villa, Flavio, 20159 Milano, IT;
Corona, Pietro, 00185 Roma, IT
Vertreter derzeit kein Vertreter bestellt
DE-Aktenzeichen 69935495
Vertragsstaaten DE, FR, GB, IT
Sprache des Dokument EN
EP-Anmeldetag 29.04.1999
EP-Aktenzeichen 998302558
EP-Offenlegungsdatum 02.11.2000
EP date of grant 14.03.2007
Veröffentlichungstag im Patentblatt 26.04.2007
IPC-Hauptklasse H01L 21/764(2006.01)A, F, I, 20051017, B, H, EP
IPC-Nebenklasse H01L 21/20(2006.01)A, L, I, 20051017, B, H, EP   

Beschreibung[en]

The present invention regards a process for manufacturing buried channels and cavities in semiconductor material wafers.

As known, presently numerous applications require channels or cavities inside a silicon substrate, for example for making suspended masses of microactuators and/or sensors of various kinds, such as speed, acceleration and pressure sensors, or for insulating electronic components.

At present, buried cavities can be made basically in different ways. According to a first solution, shown in Figure 1, two monocrystalline silicon wafers 1, appropriately excavated so as each of them presents a half-cavity, are bonded together using an adhesive layer (for example, silicon oxide 2) so that the two half-cavities form a buried cavity 3.

According to a second solution, shown in Figure 2, a wafer 1 of monocrystalline silicon, appropriately excavated so as to present final cavities 4, is bonded to a glass layer 5 (anodic bonding process).

Such solutions are costly, highly critical, have low productivity, and are not completely compatible with the usual technological phases involved in the manufacture of microelectronic components. In addition, in the solution of Figure 2, it is not always possible to make also an integrated circuit.

EP 0 890 998 teaches another solution including forming a sacrificial buried region on a substrate, epitaxially growing a semiconductor material layer comprising a polycrystalline portion above the sacrificial buried region and a monocrystalline region elsewhere, forming openings in the substrate up to the sacrificial buried region, and removing the sacrificial buried region through the openings to form a buried cavity.

A further solution is known from US-A-4 993 143, wherein a moat is formed in a wafer by the use of a mask. An oxide layer is formed on the side walls of the moat. In a further etch step a cavity is formed via the moat, which can then be overgrown in order to form a buried cavity.

The aim of the present invention is thus to provide a process that eliminates the disadvantages of the known solutions.

According to the present invention, a process for manufacturing buried cavities in semiconductor material wafers and a semiconductor material wafer are provided, as defined in Claims 1 and 12, respectively.

For an understanding of the present invention, a preferred embodiment thereof is now described, as a non-limiting example, with reference to the attached drawings, wherein:

  • Figure 1 shows a cross section through a semiconductor material wafer made according to a known solution;
  • Figure 2 presents a cross section of another known solution;
  • Figures 3 to 11 show cross sections through a semiconductor material wafer in successive manufacturing steps, according to the present invention; and
  • Figure 12 shows, on a reduced scale, the wafer obtained with the manufacturing process according to the present invention.

Figure 3 shows a wafer 10 of monocrystalline silicon formed by a substrate 11 having a surface 12. On the surface 12 an etching-aid region 13 is formed, and has a thickness preferably comprised between 450 and 1000 nm; the etching-aid region 13 is obtained, for example, by chemical vapour deposition (CVD) of a polycrystalline silicon layer and subsequent definition of the polycrystalline silicon layer, using a resist mask. The etching-aid region 13 has the function of modifying the shape of the desired cavities or channels, as explained hereinafter.

Subsequently, a thermal oxidation is carried out (Figure 4); a first pad layer 15 of silicon oxide is then grown on the etching-aid region 13 and on the surface 12 of the wafer 10 where the latter is not covered by the etching-aid region 13. The first pad layer 15 has, for example, a thickness comprised between 20 and 100 nm. Thereafter a first etch-shielding layer 16 of silicon nitride having a thickness, for example, comprised between 90 and 200 nm, and then a nucleus layer 17 of polycrystalline silicon having a thickness comprised between 1 and 2 µm are deposited. The nucleus layer 17 is preferably deposited by CVD. A thermal oxidation is then carried out, forming a second pad layer 18 of silicon oxide, having a thickness comprised, for example, between 20 and 60 nm, on the nucleus layer 17; and then a second etch-shielding layer 19 of silicon nitride is deposited, and has a thickness comprised, for example, between 90 and 200 nm. In this way, the intermediate structure of Figure 4 is obtained, which presents a stack of layers 16-19.

A resist mask 20 is then formed (Fig. 5) and covers the entire wafer 10, except for a window 21 above the etching-aid region 13. Using the resist mask 20, the second etch-shielding layer 19, the second pad layer 18, the nucleus layer 17, and the first etch-shielding layer 16 are etched in succession by dry and wet etchings. Etching ends automatically on the first pad layer 15. At the end of etching, a hole 22 extends through the stack of layers 16-19 down to the first pad layer 15. Advantageously, the width of the hole 22 is comprised between 1 and 5 µm, and its length and shape (in the direction perpendicular to the plane of the drawing) are determined by the length and shape of the etching-aid region 13 and, ultimately, by the desired characteristics of the cavity to be made.

Subsequently (Fig. 6), the resist mask 20 is removed, and the exposed surface of the nucleus layer 17 facing the hole 22 is thermally oxidized and forms an oxide portion 24 having a thickness comprised between, for example, 20 and 100 nm and joining to, without solution of continuity, the second pad layer 18.

A third etch-shielding layer 25 of silicon nitride is then deposited and has a thickness comprised preferably between 90 and 200 nm (Fig. 7) and completely coats the walls and the bottom of the hole 22. The third etch-shielding layer 25 is then anisotropically etched and is removed in the horizontal portions on the second etch-shielding layer 19 and on the bottom of the hole 22. A coating region 25' remains on the lateral walls of the hole (now indicated with 22') and joins, without solution of continuity, with the first and second etch-shielding layers 16, 19, also of silicon nitride, forming with the latter a protective structure 26, which completely envelops the second nucleus layer 17 (Fig. 8).

Next, the uncovered portion of the first pad layer 15, beneath the hole 22', is dry or wet etched, in a time controlled way, uncovering the etching-aid region 13. The intermediate structure shown in Fig. 8 is thus obtained.

The substrate 11 is then etched, in a time controlled way, using tetramethylammoniumhydroxide (TMAH) having the formula (CH3)4NOH (Fig. 9). The shape of the etching is determined by both the presence of the etching-aid region 13 and the etch directionality. In fact, since the etching-aid region 13 is of polycrystalline silicon, it is removed preferentially with respect to the substrate 11, which is of monocrystalline silicon, and determines the etch extent, parallel to the surface 12. On the other hand, with the structure of Fig. 9, where the surface 12 of the wafer has orientation <100>, the oblique etching speed, according to the orientation <111>, is much lower than the etching speed according to the orientation <100> (V<111> << V<100>), and the monocrystalline silicon of the substrate 11 is preferentially etched along the vertical.

It follows that, on the whole, etching occurs according to fronts having a width determined by the progressive removal of the etching-aid region 13, and extends in depth into the substrate 11, as shown in Figure 9, where the dashed lines and the dashed and dotted lines indicate successive etching fronts, and the arrows indicate the etching advancement direction. At the end of etching, after a preset time, dependent on the width of the etching-aid region 13, a tub shaped cavity 30 is formed in the substrate 11. In this step, the nucleus layer 17 is protected by the protective structure 26.

The wall of the cavity 30 is then thermally oxidized and forms a protective layer 31 (Fig. 10) having a thickness preferably comprised between 60 and 300 nm.

Subsequently (Fig. 11), the nitride material is etched, removing the second etch-shielding layer 19, and then the second oxide pad layer 18 is etched. Given the greater thickness of the protective layer 31, as compared to the second pad layer 19, in this step the protective layer 31 is, at most, removed only partially.

Using a resist mask, the nucleus layer 17 is suitably shaped so as to be removed everywhere, except above and around the cavity 30; in addition, the first etch-shielding layer 16 and the first pad layer 15 are etched and removed where they are exposed. Consequently, the surface 12 of the substrate 11 is once more exposed, except for at the cavity 30.

Finally (Fig. 12), epitaxial growth is carried out starting from the substrate 11 (where this is not covered) and from the nucleus layer 17. In particular, a so-called pseudo-epitaxial layer 33 is formed, formed by a monocrystalline portion 33a on the substrate 11 and a polycrystalline portion 33b on the nucleus layer 17, these portions being separated by a transitional region 33c, as shown in Figure 12. The substrate 11 and the pseudo-epitaxial layer 33 thus form a wafer 34. In addition, the epitaxial growth over the nucleus layer 17 takes place also horizontally, closing the hole 22'. Consequently, the cavity 30 is closed on all its sides and is completely embedded in the wafer 34.

The wafer 34 then undergoes further processing steps according to the devices to be made. In particular, in the polycrystalline portion 33b suspended structures are made, such as membranes, induction coils, accelerometers, etc., and in the monocrystalline portion 33a of the pseudo-epitaxial layer 33 electronic processing and control components are integrated.

The advantages of the described process are the following: first, the process enables forming closed cavities in a silicon wafer with process steps that are fully compatible with semiconductor manufacturing processes. The process does not present particular critical aspects, and enables good productivity, contained costs, and the integration of microstructures and electronic components.

Finally, it is clear that modifications and variations can be made to the process described and illustrated herein, all of which fall within the scope of the invention, as defined in the attached claims. In particular, the size, shape and number of holes 22' are suitably chosen on the basis of the size and shape of the cavity 30 to be formed and of the characteristics of the TMAH etching on the substrate 11. In particular, in the case of a hole 22' of an elongated shape, it is possible to obtain elongated channels; in the case of suspended structures of large area, it is possible to make a number of holes 22' above a same etching-aid region 13 so as to form a number of initial cavities which then join up to form a final, large size cavity parallel to the surface 12 of the substrate 11.

In addition, the thermal oxidation used to form the protective layer 31 may be omitted, and the nucleus layer 17 can be made in two steps by depositing a thin vapour-phase layer and then growing a polycrystalline layer epitaxially up to the desired thickness.

Finally, after forming the cavity 30, the removal of the second etch-shielding layer 19 and of the second pad layer 18 can be carried by wet etching, also removing the coating region 25' and the oxide portion 24.


Anspruch[de]
Verfahren zum Herstellen vergrabener Hohlräume in Halbleitermaterialscheiben, gekennzeichnet durch die Abfolge von Schritten: - Ausbilden eines Schichtstapels (16-19) auf einem einkristallinen Körper (11) aus Halbleitermaterial, wobei der Schichtstapel (16-19) eine erste Ätzabschirmungsschicht (16), eine Keimschicht (17) aus polykristallinem Silizium und eine zweite Ätzabschirmungsschicht (19) aufweist; - Ausbilden eines Fensters (22) innerhalb des Schichtstapels mit seitlich abgrenzenden Wänden; - Beschichten der seitlich abgrenzenden Wände des Fensters mit einem Abdeckungsgebiet (25'), wodurch die Keimschicht (17) von einer Schutzstruktur (26) umgeben ist und über eine Öffnung (22') abgegrenzt ist; - Ausbilden eines Hohlraums (30) im einkristallinen Körper (11) unterhalb der Keimschicht (17) durch die Öffnung hindurch; Entfernen wenigstens eines oberen Bereichs (19) der Schutzstruktur (26); und - Aufwachsen einer epitaktischen Schicht (33) auf dem einkristallinen Körper (11) und der Keimschicht (17). Verfahren nach Anspruch 1, dadurch gekennzeichnet, dass das Ausbilden eines Hohlkörpers (30) den Schritt Ätzen des einkristallinen Körpers (11) durch die Öffnung (22'), welche von der Schutzstruktur (26) abgegrenzt ist, aufweist. Verfahren nach Anspruch 1 oder 2, dadurch gekennzeichnet, dass der Ätzschritt als TMAH-Ätzung ausgeführt wird. Verfahren nach einem der Ansprüche 1-3, dadurch gekennzeichnet, dass vor dem Ausbilden einer Keimschicht (17) ein Ätzungsunterstützungsgebiet (13) direkt auf dem einkristallinen Körper (1) ausgebildet wird, wobei das Ätzungsunterstützungsgebiet unterhalb der Keimschicht (17) angeordnet wird und von der Keimschicht (17) durch die Schutzstruktur (26) getrennt ist. Verfahren nach Anspruch 4, dadurch gekennzeichnet, dass das Ätzungsunterstützungsgebiet (13) aus polykristallinem Silizium besteht. Verfahren nach Anspruch 4 oder 5, dadurch gekennzeichnet, dass die Keimschicht (17) auf dem Ätzungsunterstützungsgebiet (13) ausgebildet wird. Verfahren nach Anspruch 6, dadurch gekennzeichnet, dass die ersten und zweiten Ätzabschirmungsschichten (16, 19) und das Abdeckungsgebiet (25') aus Siliziumnitrid sind. Verfahren nach Anspruch 7, gekennzeichnet durch Ausbilden einer thermischen Oxidschicht (15. 18) unterhalb der ersten und zweiten Ätzabschirmungsschichten (16, 19) und Ausbilden thermischer Oxidgebiete (24) unterhalb des Abdeckungsgebiets (25'). Verfahren nach einem der vorangehenden Ansprüche, gekennzeichnet durch Ausbilden eines Schutzgebiets (31) auf Seitenwänden des Hohlraums (30), bevor ein oberer Bereich (19) der Schutzstruktur (26) entfernt wird. Verfahren nach Anspruch 9, dadurch gekennzeichnet, dass das Ausbilden eines Schutzgebiets (31) ein thermisches Oxidieren der Wände des Hohlraums (30) beinhaltet. Verfahren nach einem der Ansprüche 9 oder 10, dadurch gekennzeichnet, dass nach dem Ausbilden eines Schutzgebiets (31) ein Schritt zum Aufwachsen einer epitaktischen Schicht (33) ausgeführt wird, wobei der Schritt ein Ausbilden eines einkristallinen Gebiets (33a) auf dem einkristallinen Körper (11) und eines polykristallinen Gebiets (33b) auf der Keimschicht (17) beinhaltet. Scheibe (34) aus einem Halbleitermaterial, die wenigstens einen vergrabenen Hohlkörper (30) beinhaltet, der in einem einkristallinen Gebiet (11) ausgebildet ist, und an der Oberseite über eine epitaktische Schicht (33) geschlossen ist, wobei die epitaktische Schicht (33) einen polykristallinen Bereich (33b) oberhalb des vergrabenen Hohlkörpers (30) und ein einkristallines Gebiet (33a) auf dem einkristallinen Gebiet (11) aufweist, gekennzeichnet durch eine Keimschicht (17) aus polykristallinem Silizium, die sich entlang des Hohlkörpers erstreckt und von einer Schutzstruktur (26) umgeben ist, wobei die Schutzstruktur (26) eine dem Hohlkörper gegenüberliegende Ätzabschirmungsschicht (16) sowie ein eine Öffnung (22') in der Keimschicht (17) abgrenzendes Abdeckungsgebiet (25') beinhaltet.
Anspruch[en]
A process for manufacturing buried cavities in semiconductor material wafers, characterized, in sequence, by the steps of: - forming on a monocrystalline body (11) of semiconductor material, a layer stack (16-19) comprising a first vetch-shielding layer (16), a nucleus layer (12) of polycrystalline-silicon, and a second etch-shielding layer (19) ; - forming, in said layer stacks' a window (22) having side delimiting walls; - coating said side delimiting walls of said window with a coating region (25'), thereby said nucleus layer (17) being surrounded by a protective structure (26) and delimiting an opening (22'); - forming a cavity (30) in said monocrystalline body (11) beneath said nucleus layer (17) through said opening; - removing at least a top portion (19) of said protective structure (26); and - growing an epitaxial layer (33) on said monocrystalline body (11) and said nucleus layer (17). A process according to claim 1, characterized in that said step of forming a cavity (30) comprises the step of etching said monocrystalline body (11) through said opening (22') delimited by said protective structure (26). A process according to claim 1 or 2, characterized in that said etching step is carried out by TMAH-etching. A process according to any of claims 1-3, characterized in that, before said step of forming a nucleus layer (17), the step is carried out of forming an etching-aid region (13) directly on said monocrystalline body (1), said etching-aid region being arranged beneath said nucleus layer (17) and being separated from said nucleus layer (17) by said protective structure (26). A process according to claim 4, characterized in that said etching-aid region (13) is of polycrystalline silicon. A process according to claim 4 or 5, characterized in that said nucleus layer (17) is formed. A process according to claim 6, characterized in that said first and second etch-shielding layers (16, 19) and said coating region (25') are of silicon nitride. A process according to claim 7, characterized by the step of forming a thermal oxide layer (15, 18) beneath said first and second etch-shielding layers (16, 19) and forming thermal oxide regions (24) beneath said coating region (25'). A process according to any of the foregoing Claims, characterized by the step of forming a protective region (31) on walls of said cavity (30), before removing a top portion (19) of said protective structure (26). A process according to claim 9, characterized in that said step of forming a protective region (31) comprises the step of thermally oxidizing said walls of said cavity (30). A process according to any of claims 9 or 10, characterized in that after forming a protective region (31), a step of growing an epitaxial layer (33) is carried out, said step comprising forming a monocrystalline region (33a) on said monocrystalline body (11), and a polycrystalline region (33b) on said nucleus layer (17). A wafer (34) of semiconductor material, comprising at least one buried cavity (30) formed in a monocrystalline region (11) and closed at the top by an epitaxial layer (33) comprising a polycrystalline portion (33b) above said buried cavity (30) and a monocrystalline region (33a) on said monocrystalline region (11) characterized by a nucleus layer (17) of polycrystalline-silicon extending over said cavity and surrounded by a protective structure (26) including an etch-shielding layer (16) facing the cavity and a coating region (25') delimiting an opening (22') in the nucleus layer (17).
Anspruch[fr]
Procédé pour fabriquer des cavités enterrées dans des plaquettes de matériau semi-conducteur, caractérisé, séquentiellement, par les étapes suivantes : - former sur un corps monocristallin (11) de matériau semi-conducteur, une pile de couches (16 à 19) comprenant une première couche de protection contre la gravure (16), une couche de noyau (17) de silicium polycristallin et une deuxième couche de protection contre la gravure (19) ; - former, dans ladite pile de couches, une fenêtre (22) ayant des parois délimitant les côtés ; - revêtir d'une région de revêtement (25')lesdites parois délimitant les côtés de ladite fenêtre, ladite couche de noyau (17) étant de ce fait entourée d'une structure protectrice (26) délimitant une ouverture (22') ; - former une cavité (30) dans ledit corps monocristallin (11) au-dessous de ladite couche de noyau (17) à travers ladite ouverture ; - enlever au moins une portion supérieure (19) de ladite structure protectrice (26) ; et - former par croissance une couche épitaxiée (33) sur ledit corps monocristallin (11) et ladite couche de noyau (17). Procédé selon la revendication 1, caractérisé en ce que ladite étape consistant à former une cavité (30) comprend l'étape consistant à graver ledit corps monocristallin (11) à travers ladite ouverture (22') délimitée par ladite structure protectrice (26). Procédé selon la revendication 1 ou 2, caractérisé en ce que ladite étape de gravure est effectuée par gravure TMAH. Procédé selon l'une quelconque des revendications 1 à 3, caractérisé en ce que, avant ladite étape consistant à former une couche de noyau (17), il est effectué une étape consistant à former une région d'assistance à la gravure (13) directement sur ledit corps monocristallin (1), ladite région d'assistance à la gravure étant disposée au-dessous de ladite couche de noyau (17) et étant séparée de ladite couche de noyau (17) par ladite structure protectrice (26). Procédé selon la revendication 4, caractérisé en ce que ladite région d'assistance à la gravure (13) est de silicium polycristallin. Procédé selon la revendication 4 ou 5, caractérisé en ce qu'il est formé ladite couche de noyau (17). Procédé selon la revendication 6, caractérisé en ce que lesdites première et deuxième couches de protection contre la gravure (16, 19) et ladite région de revêtement (25') sont de nitrure de silicium. Procédé selon la revendication 7, caractérisé par l'étape consistant à former une couche d'oxyde thermique (15, 18) au-dessous desdites première et deuxième couches de protection contre la gravure (16, 19) et à former des régions d'oxyde thermique (24) au-dessous de ladite région de revêtement (25'). Procédé selon l'une quelconque des revendications précédentes, caractérisé par l'étape consistant à former une région protectrice (31) sur des parois de ladite cavité (30) avant d'enlever une portion supérieure (19) de ladite structure protectrice (26). Procédé selon la revendication 9, caractérisé en ce que ladite étape de formation d'une région protectrice (31) comprend l'étape consistant à oxyder thermiquement lesdites parois de ladite cavité (30). Procédé selon l'une quelconque des revendications 9 ou 10, caractérisé en ce que, après la formation d'une région protectrice (31), il est effectué une étape consistant à former par croissance une couche épitaxiée (33), ladite étape comprenant la formation d'une région monocristalline (33a) sur ledit corps monocristallin (11) et une région polycristalline (33b) sur ladite couche de noyau (17). Plaquette (34) de matériau semi-conducteur, comprenant au moins une cavité enterrée (30) formée dans une région monocristalline (11) et fermée au dessus par une couche épitaxiée (33) comprenant une portion polycristalline (33b) au-dessus de ladite cavité enterrée (30) et une région monocristalline (33a) sur ladite région monocristalline (11), caractérisée par une couche de noyau (17) de silicium polycristallin s'étendant sur ladite cavité et étant entourée d'une structure protectrice (26) incluant une couche de protection contre la gravure (16) en face de la cavité et une région de revêtement (25') délimitant une ouverture (22') dans la couche de noyau (17).






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