Field of the Invention
This invention relates generally to frequency synthesizers,
and more particularly to a fractional phase detector that increases the overall
resolution of an integer phase-locked loop such that the quantization error of the
integer phase-locked loop is corrected.

Description of the Prior Art
Frequency synthesizers using analog circuit techniques
are well known in the art. Conventional RF frequency synthesizer architectures are
analog-intensive and generally require a low loop bandwidth to reduce the familiar
and well-known reference or compare frequency spurs. Low loop bandwidths are acceptable
for RF-BiCMOS and RF-SiGe processes with weak digital capabilities.

Modern deep sub-micron CMOS processes and their RF-CMOS
derivatives, however, are not very compatible with frequency synthesizer designs
using analog circuit techniques. The conventional PLL-based frequency synthesizers
generally comprise analog-intensive circuitry that does not work very well in a
voltage-headroom-constrained aggressive CMOS environment. Such frequency synthesizers
do not take advantage of recently developed high density digital gate technology.

Newer frequency synthesizer architectures have used sigma-delta
modulated frequency divider techniques to randomize the above discussed frequency
spurs by randomizing the spurious content at the cost of increased noise floor.
These techniques have not significantly reduced the undesirable analog content.
Other frequency synthesizer architectures have used direct digital synthesis (DDS)
techniques that do not work at RF frequencies without a frequency conversion mechanism
requiring an analog solution. Further, previous all-digital PLL architectures rely
on an over-sampling clock. Such architectures cannot be used at RF frequencies.

In view of the foregoing, it is highly desirable to have
a technique to implement a digitally-intensive frequency synthesizer architecture
that is compatible with modern CMOS technology and that has a phase quantization
resolution of better than +/- n to accommodate wireless applications.

Summary of the Invention
The present invention is directed to a digital fractional
phase detector for an all-digital phase domain PLL frequency synthesizer that is
compatible with deep sub-micron CMOS processes. The all-digital phase domain PLL
frequency synthesizer accommodates direct frequency/phase modulation transmission
to remove the requirement for an additional transmitting modulator normally associated
with wireless digital transmitters. This is accomplished by operating the PLL entirely
in the phase domain with maximum digital processing content such that the loop can
be of high-bandwidth of "type 1" without the need for a loop filter. A "type 1"
PLL loop, as used herein, means a loop having only one integrating pole in the feedback
loop. Only one integrating pole exists due to the VCO frequency-to-phase conversion.
It is possible therefore, to eliminate a low-pass filter between the phase detector
and the oscillator tuning input, resulting in a high bandwidth and fast response
of the PLL loop.

According to one embodiment, the all-digital phase domain
PLL frequency synthesizer contains only one major analog component, a digitally-controlled
2.4 GHz voltage controlled oscillator (VCO or dVCO). The PLL loop is an all-digital
phase domain architecture whose purpose is to generate the 2.4 GHz high frequency
*f*_{osc}
for the "BLUETOOTH" standard. The underlying frequency stability of the system
is derived from a reference crystal oscillator, such as a 13 MHz TCXO for the global
system for mobile communications (GSM) system. The phase of the VCO output is obtained
by accumulating the number of significant (rising or falling) edge clock transitions.
The phase of the reference oscillator is obtained by accumulating a frequency control
word on every significant (rising or falling) edge of the reference oscillator output
that is re-clocked via the VCO output. As used herein, "significant edge" means
either a "rising" or a "falling" edge. A ceiling element continuously adjusts a
reference phase value associated with the accumulated frequency control word by
rounding off to the next integer (alternatively, truncating fractional bits necessary)
to compensate for fractional-period delays caused by re-clocking of the reference
oscillator by the VCO output. The phase error signal is then easily obtained by
using a simple arithmetic subtraction of the VCO phase from the adjusted reference
phase on every significant edge of the re-clocked reference oscillator output. The
phase error signal can then be used as the tuning input to the digitally-controlled
VCO directly via a gain element associated with the PLL loop operation.

Due to the VCO edge counting nature of the PLL (all-digital
phase domain architecture), the phase quantization resolution cannot be better than
+/- n radians of the frequency synthesizer VCO clock. The present digital fractional
phase detector is capable of accommodating a quantization scheme to measure fractional
delay differences between the significant edge of the frequency synthesizer VCO
clock and an external reference oscillator clock. According to one embodiment, the
digital fractional phase detector has a time-to-digital converter having a resolution
determined by an inverter delay associated with a given CMOS process. The digital
fractional phase is determined by passing the frequency synthesizer VCO clock through
a chain of inverters such that each inverter output will produce a clock pulse slightly
delayed from that of the immediately previous inverter. The resultant staggered
clock phases would then be sampled by the same reference clock.

In one aspect of the invention, a digital fractional phase
detector system is provided that allows fast design turn-around using automated
CAD tools.

In still another aspect of the invention, a digital fractional
phase detector system is provided to implement an all-digital phase domain PLL frequency
synthesizer having much less undesirable parameter variability than normally associated
with analog circuits.

In yet another aspect of the invention, a digital fractional
phase detector system is provided to implement an all-digital phase domain PLL frequency
synthesizer having enhanced testability features.

In yet another aspect of the invention, a digital fractional
phase detector system is provided to implement an all-digital phase domain PLL frequency
synthesizer that requires desirably low silicon area to physically implement.

In yet another aspect of the invention, a digital fractional
phase detector system is provided to implement an all-digital phase domain PLL frequency
synthesizer that requires lower power than conventional frequency synthesizers.

In still another aspect of the invention, a digital fractional
phase detection system is provided to implement an all-digital phase domain PLL
frequency synthesizer having direct frequency/phase modulation transmission capability
to minimize system transmitter requirements.

In still another aspect of the invention, a digital fractional
phase detection system is provided to implement an all-digital phase domain PLL
frequency synthesizer that accommodates the "BLUETOOTH" communication protocol.

In yet another aspect of the invention, a digital fractional
phase detection system is provided to increase the overall resolution of an integer
phase-locked loop such that the quantization error of the integer phase-locked loop
is corrected.

Brief Description of the Drawings
Other aspects and features of the present invention and
many of the attendant advantages of the present invention will be readily appreciated
as the same become better understood by reference to the following detailed description
when considered in connection with the accompanying drawings in which like reference
numerals designate like parts throughout the figures thereof and wherein:

- Figure 1 illustrates an all-digital PLL synthesizer;
- Figure 2 is a simple block diagram illustrating a quantization scheme for fractional-phase
detection associated with the synthesizer depicted in Figure 1;
- Figure 3 is a timing diagram illustrating a frequency reference clock signal
and a VCO clock signal for a negative fractional-phase;
- Figure 4 is a timing diagram illustrating a frequency reference clock signal
and a VCO clock signal for a positive fractional-phase;
- Figure 5 is a schematic diagram illustrating a time-to-digital converter according
to one embodiment of the present invention and that is suitable to implement the
quantization scheme depicted in Figure 2;
- Figure 6 is a timing diagram associated with the time-to-digital converter shown
in Figure 5;
- Figure 7 illustrates an example of integer-loop quantization error for a simplified
case of the fractional-N frequency division ratio of N = 2 R; and
- Figure 8 is a simplified schematic diagram illustrating a scheme for correcting
the integer-loop quantization error &egr;(k) by means of a fractional phase detector
(PDF) for the all-digital PLL synthesizer shown in Figure 1.

While the above-identified drawing figures set forth alternative
embodiments, other embodiments of the present invention are also contemplated, as
noted in the discussion. In all cases, this disclosure presents illustrated embodiments
of the present invention by way of representation and not limitation. Numerous other
modifications and embodiments can be devised by those skilled in the art which fall
within the scope and spirit of the principles of this invention.

Detailed Description of the Preferred Embodiments
Figure 1 illustrates an all-digital PLL synthesizer 100.
The synthesizer 100 naturally combines transmitter frequency modulation capability
with a wideband, all-digital PLL modulation technique to maximize digitally-intensive
implementation by operating in a synchronous phase domain. The PLL loop utilizes
an all-digital phase domain architecture capable of generating the 2.4 GHz high
frequency *f*_{osc}
for the "BLUETOOTH" standard band. Accordingly, the all-digital phase domain
PLL frequency synthesizer 100 depicted in Figure 1 contains only one major analog/RF
component, a digitally-controlled 2.4 GHz voltage controlled oscillator (dVCO) 104,
being a portion of a numerically-controlled oscillator (NCO) 103, that also comprises
a gain element 105. The underlying frequency stability of the synthesizer 100 is
derived from a frequency reference crystal oscillator 110, such as a 13 MHz TCXO
for the GSM system.

The phase &thgr;*
*_{v}
(*iT*_{v}
) of the dVCO 104 clock signal, CKV 114, with period *T*_{v}
, at time instances i*T*_{v}
, where i is an integer, is obtained by accumulating the number of rising- or
falling-edge clock transitions generated via a sinusoidal-to-digital converter 106.
$${\mathrm{\&thgr;}}_{v}\left({iT}_{v}\right)={\displaystyle \sum _{t=0}^{i\u2022{T}_{v}}}{f}_{v}\left(t\right)\phantom{\rule{4em}{0ex}}\left(\times ,2,,\mathrm{\&pgr;},\u2022,\mathit{rad}\right)$$

Without use of frequency reference retiming (described
herein below), the phase *&thgr;*_{r}
(*kT*_{r}
) of a frequency reference clock, *FREF,* provided by the reference crystal
oscillator (*FREF*) 110, with period *T*_{r}
, at time instances *kT*_{r}
where *k* is another integer, is obtained by accumulating 102 the frequency
control word (FCW 116) on every rising (or falling) edge of the frequency reference
clock *FREF*.
$${\mathrm{\&thgr;}}_{r}\left(k,,{T}_{r}\right)=\mathit{FCW}\u2022k\u2022{T}_{r}\phantom{\rule{4em}{0ex}}\left(\times ,2,,\mathrm{\&pgr;},\u2022,\mathit{rad}\right)$$

The PLL operation achieves, in a steady-state condition,
a zero averaged phase difference between the dVCO 104 &thgr;*
*_{v}
(*iT*_{v}
) and the reference crystal oscillator 110 &thgr;*
*_{r}
(*kT*_{r}
) phases. Equation (3) below shows the clock period relationship in the mean
sense.
$$\mathit{FCW}={N}_{i}+{N}_{f}={T}_{r}/{\stackrel{\u203e}{T}}_{v}$$

The present invention is not so limited however, and it shall be readily understood
that *FCW* 116 can be comprised of only an integer or an integer (*N*_{i}
) and fractional (*N*_{f}
) parts.

As stated herein before, there is no need for a frequency
detection function within the phase detector when operating the PLL loop in the
phase domain. This feature importantly allows "type 1" operation of the PLL, where
it is possible to eliminate a low-pass filter between the phase detector and the
oscillator (dVCO 104), resulting in a high-bandwidth and fast response of the PLL
loop.

The dVCO 104 and the reference crystal oscillator 110 clock
domains are entirely asynchronous, making it difficult to physically compare the
two digital phase values &thgr;*
*_{v}
(*iT*_{v}
) and &thgr;*
*_{r}
(*kT*_{r}
) at different time instances *iT*_{v}
and *kT*_{r}
. Mathematically, &thgr;*
*_{v}
(*iT*_{v}
) and &thgr;*
*_{r}
(*kT*_{r}
) are discrete-time signals with incompatible sampling times and cannot be directly
compared without some sort of interpolation. The present inventors recognized therefore,
it is imperative that any digital-word comparison be performed in the same clock
domain. This function is achieved by over-sampling the *FREF* reference oscillator
110 by the high-rate dVCO 104 output CKV 114, and using the resulting frequency
reference clock *CKR* 112 to accumulate via accumulator 102 the reference phase
&thgr;*
*_{r}
·(*kT*_{r}
) as well as to synchronously sample, via latch/register 120, the high-rate
dVCO 104 phase &thgr;*
*_{v}
(*iT*_{v}
). Since the foregoing phase comparison is performed synchronously at the rising
edge of CKR 112, equations (1) and (2) can now be rewritten as follows:
$${\mathrm{\&thgr;}}_{v}\left(k\right)={\displaystyle \sum _{t=0}^{k\u2022{T}_{r}}}{f}_{v}\left(t\right)\phantom{\rule{4em}{0ex}}\left(\times ,2,,\mathrm{\&pgr;},\u2022,\mathit{rad}\right)$$
$${\mathrm{\&thgr;}}_{v}\left(k\right)=\mathit{FCW}\u2022k\u2022{T}_{r}+\mathrm{\&egr;}\left(k\right)\phantom{\rule{4em}{0ex}}\left(\times ,2,,\mathrm{\&pgr;},\u2022,\mathit{rad}\right)$$

where the index k is the kth transition of the re-timed reference clock
*CKR* 112 and contains an integer number of *CKV* 114 clock transitions;
and *&egr;*(*k*) is the integer-loop quantization error, in the range
of &egr;∈(0,1), that could be further corrected by other means, such as
a fractional phase detector 200 discussed in more detail herein below with reference
to Figures 2-6.

In view of the above, the integer phase detector in the
synchronous digital phase environment can now be realized as a simple arithmetic
subtraction via combinatorial element 122 of the dVCO 104 phase from the reference
phase performed every rising edge of the CKR clock 112.
$${\mathrm{\&thgr;}}_{d}\left(k\right)={\tilde{\mathrm{\&thgr;}}}_{r}\left(k\right)-{\mathrm{\&thgr;}}_{v}\left(k\right)$$

The reference re-timing operation can be recognized as
a quantization in the dVCO 104 *CKV* 114 clock transitions integer domain,
where each *CKV* 114 clock transition rising edge is the next integer. Since
the synthesizer 100 must be time-causal, quantization to the next *CKV* 114
clock transition rising edge (next integer), rather than the closest transition
(rounding-off to the closest integer), can only be realistically performed. This
limitation is then compensated for in the phase domain by the ceiling element 108
associated with the reference phase since the reference phase &thgr;*
*_{r}
(*k*) is generally a fixed-point arithmetic signal having a sufficiently
large fractional part to achieve the required frequency resolution as set forth
in Equation 3 above. As stated herein before, a ceiling element 108 continuously
adjusts a reference phase value associated with the accumulated frequency control
word by rounding to the next integer (alternatively, truncating the fractional bits),
thereby compensating for delays caused by re-clocking of the reference oscillator
110 by the VCO output *CKV* 114. The ceiling operation (demonstrated via Equation
7) could be easily implemented by discarding the fractional bits and incrementing
the integer bits. This technique, however, improperly handles the case when the
fractional part is zero, but has no practical consequences. Those skilled in the
art will appreciate that this truncation process achieves a timing correction since
phase is a characteristic that can be used to describe a time progression. The phase
resolution, however, cannot be better than +/- n radians of the dVCO 104 clock,
even though the foregoing integer-loop quantization error &egr; due to reference
phase retiming illustrated by Equation 5 is compensated by next-integer rounding
operation (ceiling) of the reference phase.
$${\tilde{\mathrm{\&thgr;}}}_{r}\left(k\right)=\lceil {\mathrm{\&thgr;}}_{r}\left(k\right)\rceil $$

Jumping now to Figure 7, an example of integer-loop quantization
error &egr; is illustrated for a simplified case of the frequency division ratio
of *N* = 2R. Unlike &egr;(*k*), which represent rounding to the
"next" VCO edge, &phgr;(*k*) is the fractional phase error; and it represents
rounding to the "closest" VCO edge.

Moving now to Figure 2, a simple block diagram illustrates
a digital fractional phase detector system 200 according to one embodiment of the
present invention. The system 200 is capable of accommodating a quantization scheme
to measure fractional (sub-Tv) delay differences between the significant edge of
the dVCO 104 clock CKV 114 and the *FREF* oscillator 110 reference clock 112.
The system 200 uses a time-to-digital converter (TDC) 201 with a resolution of &Dgr;*t*_{ref}
and expresses the time difference as a digital word. Due to the dVCO 104 edge
counting nature of the PLL, it can be appreciated that the phase quantization resolution
cannot be better than +/- n radians as stated above. A much finer phase resolution
however, is required for wireless applications such as "BLUETOOTH." Such finer resolution
must be achieved without forsaking the requisite digital signal processing capabilities.

Figure 8 is a simplified schematic diagram illustrating
a scheme for correcting the integer-loop quantization error &egr;(k) by means
of a fractional phase detector (PDF) 804 for the all-digital PLL synthesizer 100
shown in Figure 1. The phase output, PHD 802, of the integer part of the PLL-loop
800, contains the fractional part of the accumulated FCW word 116, *frac*(*&thgr;*_{r}
), if the desired fractional division ratio FCW 116 is generally fractional-N.
A preferred alternative method by which *frac*(&thgr;*
*_{r}
) is subtracted from both the integer reference phase &thgr;*
*_{r}
and the fractional correction &egr;(*k*) is discussed herein below with
reference to Figures 2-6, and is captured schematically on Figure 1.

The solution illustrated in Figure 2 measures the one-sided
fractional (sub-*T*_{v}
) delay difference between the dVCO 104 clock CKV 114 and the *FREF* oscillator
110 clock 112 to express the time difference as a digital word &egr; 202. According
to one embodiment, the maximum readily achievable timing resolution of the digital
fractional phase detector 200 is determined by an inverter delay associated with
a given CMOS process, and is about 40 psec for the C035.1 CMOS process developed
by Texas Instruments Incorporated of Dallas, Texas. The digital fractional phase
is determined by passing the dVCO 104 clock CKV 114 through a chain of inverters
(such as shown in Figure 5), such that each inverter output would produce a clock
pulse slightly delayed from that of the immediately previous inverter. The resultant
staggered clock phases would then be sampled by the same reference clock.

As seen in Figures 3 and 4, position of the detected transition
from 1 to 0 would indicate a quantized time delay &Dgr;*T*_{r}
between the *FREF* 110 sampling edge and the rising edge 302 of the dVCO
clock, CKV 114 in &Dgr;*t*_{res}
multiples; and position of the detected transition from 0 to 1 would indicate
a quantized time delay &Dgr;*T*_{f}
between the *FREF* 110 sampling edge and the falling edge 400 of the dVCO
clock, CKV 114. Because of the time-causal nature of the foregoing digital fractional
phase detection process, both time delay values &Dgr;*T*_{r}
and &Dgr;*T*_{f}
must be interpreted as non-negative. This is fine if &Dgr;*T*_{r}
is smaller than &Dgr;*T*_{f}
since this situation corresponds to the negative phase error of the classical
PLL loop in which the VCO edge is ahead of the reference edge and, therefore, the
phase sign has to be negated. If &Dgr;*T*_{r}
is greater than &Dgr;*T*_{f}
however, the situation becomes problematic since the situation now corresponds
to the positive phase error of the classical PLL loop. The time lag between the
reference edge *FREF* 110 and the following rising edge of CKV 114 must be
based on the available information regarding the delay between the preceding rising
edge of *CKV* 114 and the reference edge *FREF* 110 as well as the clock
half-period which can be expressed as a difference as shown by Equation 8 below.
$${\mathit{T}}_{\mathit{v}}\mathit{/}\mathit{2}=\begin{array}{cc}\{\mathrm{\&Dgr;}{t}_{r}-\mathrm{\&Dgr;}{t}_{f}& \mathrm{\&Dgr;}{t}_{r}\ge \mathrm{\&Dgr;}{t}_{f}\\ \{\mathrm{\&Dgr;}{t}_{f}-\mathrm{\&Dgr;}{t}_{r}& \mathit{otherwise}\end{array}$$

The foregoing analysis is summarized in Equation 9 below,
where &Dgr;*t*_{frac}
is the digital fractional phase detector error.
$$\mathrm{\&Dgr;}{t}_{\mathit{frac}}=\{\begin{array}{cc}-\mathrm{\&Dgr;}{t}_{r}\hfill & \mathrm{\&Dgr;}t\le \mathrm{\&Dgr;}{t}_{f}\\ \mathrm{\&Dgr;}{t}_{r}-2\u2022\mathrm{\&Dgr;}{t}_{f}\hfill & \mathit{otherwise}\end{array}$$

The period-normalized fractional phase is then described by Equation 10 as:
$$\varphi F=\mathrm{\&Dgr;}{t}_{\mathit{frac}}/{T}_{v}$$

In the instant embodiment, where the integer phase detector output, &thgr;*
*_{t}
, is used, the fractional phase &phgr;*
*_{F}
is not needed. Instead, &Dgr;*t*_{r}
is used to calculate the &egr;(*k*) correction of Equation 5 that is
positive and &egr;∈(0,I). &Dgr;*t*_{r}
has to be normalized by dividing it by the clock period, in order to properly
combine it with the integer phase detector output, &thgr;*
*_{il}
.
$$\mathrm{\&egr;}\left(k\right)=\mathrm{\&Dgr;}{t}_{r}\left(k\right)/{T}_{v}\left(k\right)=\{\begin{array}{cc}\mathrm{\&Dgr;}{t}_{r}/2(\mathrm{\&Dgr;}{t}_{f}-\mathrm{\&Dgr;}{t}_{r})& \mathrm{\&Dgr;}{t}_{r}<\mathrm{\&Dgr;}{t}_{f}\\ \mathrm{\&Dgr;}{t}_{r}/2(\mathrm{\&Dgr;}{t}_{r}-\mathrm{\&Dgr;}{t}_{f})& \mathit{otherwise}\end{array}$$

When the dVCO 104 clock period *T*_{v}
is an integer division of the frequency reference clock period *T*_{r}
, the *&egr;*(*k*) samples are seen to be constant. The
*&egr;*(*k*) samples increase linearly within the modulo (0,1) range
where this ratio is fractional. In view of the foregoing, a simple pattern can therefore
be easily predicted in digital form that closely corresponds mathematically to the
well-known analog fractional phase compensation scheme of fractional-N PLL frequency
synthesizers. Figure 7 illustrates an example of the predicted behavior of &egr;(*k*).
$$\tilde{\mathrm{\&egr;}}\left(k\right)=\mathrm{\&egr;}\left(k\right)-\mathit{fract}\left({\mathrm{\&thgr;}}_{r},\left(k\right)\right)$$

The composite phase error &thgr;*
*_{e}
(*k*) is obtained through correcting the integer-valued *&thgr;*_{il}
(*k*) by fractional-division-ratio-corrected &egr;(*k*) as shown
in Equation 13.
$${\mathrm{\&thgr;}}_{e}\left(k\right)={\mathrm{\&thgr;}}_{d}\left(k\right)-\tilde{\mathrm{\&egr;}}\left(k\right)$$

The fractional phase detector output &egr;(*k*)
or &phgr;*
*_{F}
(*k*) sequence can be easily compared on a bit-by-bit basis; and since
the expected output pattern is known in advance and is now in the digital format,
a better alternative of a Viterbi sequence detection or a matched filter could be
used. In such a scenario, the space difference between the observed and expected
patterns could be output as the fractional phase error. This solution provides a
system with less reference feedthrough and lower overall error.

The present PLL loop operation can be further enhanced
by taking advantage of the predictive capabilities of the all-digital PLL loop.
The dVCO 104, for example, does not necessarily have to follow the modulation FCW
116 command with the normal PLL loop response. In one embodiment, where the dVCO
104 control and the resulting phase error measurement are in numerical format, it
is easy to predict the current *K*_{VCO}
gain of the dVCO 104 by simply observing the past phase error responses to
the NCO corrections. With a good estimate of the *K*_{vco}
gain, the normal NCO control could be augmented with the "open loop" instantaneous
frequency jump estimate of the new FCW 116 command. It can be appreciated that the
resulting phase error should be very small and subject to the normal closed PLL
loop correction transients.

Since the time response of this "type 1" PLL is very fast
(less than 1 µsec), the prediction feature is less important for channel hopping,
where the allowed time is much greater. The foregoing prediction feature is, however,
essential to realize the direct frequency synthesizer modulation in the Gaussian
*frequency shift keying* GFSK modulation scheme of "BLUETOOTH" or GSM.

Figure 5 is a schematic diagram illustrating a time-to-digital
converter 500 according to one embodiment of the present invention and that is suitable
to implement the time delay quantization scheme depicted in Figure 2. The time-to-digital
converter 500 includes a plurality of inverter delay elements 502 and latch/registers
504. As the dVCO clock CKV 114 continues to run, the CKV 114 delayed vector is latched
into the storage elements (latch/registers 504). It is readily apparent that the
converter can be formulated from any desired number of inverter delay elements 502
and latch/registers 504, within certain physical limitations, so long as the total
delay of the inverter array sufficiently covers the CKV 114 clock period. The delayed
vector characteristics are therefore dependent upon the total number of inverter
delay elements 502, delay values of individual inverter delay elements 502, and
associated latch/registers 504 used to formulate the time-to-digital converter 500.
During a positive transition (enumerated 602 in Figure 6) of the reference clock
*FREF* 110, each of the latch/registers 504 will be queried in order to obtain
a snapshot of the quantized fractional phase difference between the dVCO 104 clock
signal CKV 114 phase and the reference clock *FREF* 110 signal phase. The accuracy
of the snapshot or indication of the fractional phase difference can be seen to
depend upon the single inverter delay elements.

Figure 6 is a timing diagram 600 associated with the time-to-digital
converter 500 shown in Figure 5. During a positive transition 602 of the reference
oscillator *FREF* 110, the plurality of latch/registers 504 are accessed to
obtain a snapshot 604 of the delayed replicas of the dVCO clock *CKV* 114 relative
to the rising edge of the reference oscillator *FREF* 110. The snapshot 604
can be seen to express the time difference as a digital word. With continued reference
to Figures 3 and 4, the timing pulses 304, 404 represent dVCO output clock
*CKV* 114 cycles that are captured in the latch/registers 504 during each significant
transition of the *FREF* clock 110. The foregoing digital word is then used
by the frequency synthesizer 100 to compensate for phase differences between the
significant edge of the dVCO clock *CKV* 114 and the reference oscillator
*FREF* 110 as discussed herein above with reference to both Figures 2-4 and
equations 8-13.

In view of the above, it can be seen the present invention
presents a significant advancement in the art of RF synthesizer circuits and associated
methods. This invention has been described in considerable detail in order to provide
those skilled in the RF synthesizer art with the information need to apply the novel
principles and to construct and use such specialized components as are required.
In view of the foregoing descriptions, it should be apparent that the present invention
represents a significant departure from the prior art in construction and operation.
However, while particular embodiments of the present invention have been described
herein in detail, it is to be understood that various alterations, modifications
and substitutions can be made therein without departing in any way from the spirit
and scope of the present invention, as defined in the claims which follow. For example,
while certain embodiments set forth herein illustrate various hardware implementations,
the present invention shall be understood to also parallel structures and methods
using software implementations as set forth in the claims.